參數(shù)資料
型號： MV80C51C-20R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44
封裝： 1.40 MM HEIGHT, QFP-44
文件頁數(shù)： 103/170頁
文件大?。?/td> 4133K
代理商： MV80C51C-20R
38
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
9.3.2
EIMSK – External Interrupt Mask Register
Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA)
define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activ-
ity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of
External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
9.3.3
EIFR – External Interrupt Flag Register
Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it.
This flag is constantly zero when INT0 is configured as a level interrupt.
Table 9-2.
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
7
65
43
2
1
0
–
–INTO
EIMSK
Read/Write
RRR
RR
R/W
Initial Value
0
Bit
7
65
43
2
1
0
–
–INTF0
EIFR
Read/Write
RRR
RR
R/W
Initial Value
0
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