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參數(shù)資料
| 型號： | MV80C51T-20D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1.40 MM HEIGHT, QFP-44 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 3152K |
| 代理商： | MV80C51T-20D |
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85
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the phase
correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the
output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 12-7 OCnx has a transition from high to low even though there is no compare match. The
point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without compare
match.
●
OCRnx changes its value from MAX, like in Figure 12-7. When the OCR0A value is MAX the OCn pin value is the same
as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCnx value at MAX must
correspond to the result of an up-counting compare match.
●
The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the compare match and
hence the OCnx change that would have happened on the way up.
12.7
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the
following figures. The figures include information on when interrupt flags are set. Figure 12-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct
PWM mode.
Figure 12-8. Timer/Counter Timing Diagram, no Prescaling
Figure 12-9 shows the same timing data, but with the prescaler enabled.
Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
MAX - 1
clkI/O
(clkI/O/1)
TCNTn
TOVn
clkTn
MAX
BOTTOM
BOTTOM + 1
MAX - 1
clkI/O
(clkI/O/8)
TCNTn
TOVn
clkTn
MAX
BOTTOM
BOTTOM + 1
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