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參數(shù)資料
| 型號： | MVTX2801 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| 中文描述： | 非托管4端口1000 Mbps以太網(wǎng)交換機(jī) |
| 文件頁數(shù)： | 14/106頁 |
| 文件大?。?/td> | 1455K |
| 代理商： | MVTX2801 |
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MVTX2801
Data Sheet
14
Zarlink Semiconductor Inc.
As at the transmit end, each of the 4 ports has time slots devoted solely to reading data from memory at the address
calculated by port control. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address.
On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO.
After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple
buffer release requests.
The frame is transmitted from the TxFIFO to the line.
3.2 Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop
can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is
dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the
multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is
not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in
the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast
frames). There are 4 multicast queues for each of the 4 Gigabit ports.
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
4.0 Memory Interface
4.1 Overview
The figure below illustrates the first part of the ZBT-SRAM interface for the MVTX2801. As shown, a 64 bit bus
ZBT-SRAM bank A is used for Tx/RxDMA access. Because the clock frequency is 133 MHz, the total memory
bandwidth is 64-bits x 133 MHz = 8.5 Gbps, for frame data buffer (FDB) access.
Figure 3 - SRAM Interface Block Diagram (DMAs for Gigabit Ports)
TX DMA
2-3
TX DMA
0-1
RX DMA
2-3
RX DMA
0-1
ZBT-SRAM Bank A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MVTX2801AG | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802 | Managed 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802AG | Managed 4-Port 1000 Mbps Ethernet Switch |
| MVTX2803 | Unmanaged 8-Port 1000 Mbps Ethernet Switch |
| MVTX2803AG | Unmanaged 8-Port 1000 Mbps Ethernet Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MVTX2801A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 4 port Gigabit Ethernet switch |
| MVTX2801AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Managed 4 port Gigabit Ethernet switch |
| MVTX2802AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 4-Port 1000 Mbps Ethernet Switch |
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