參數(shù)資料
型號: MVTX2804AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: 8-Port 1000 Mbps Ethernet Distributed Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝: 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù): 18/174頁
文件大小: 2249K
代理商: MVTX2804AG
MVTX2804
Data Sheet
18
Zarlink Semiconductor Inc.
Figure 2 - Overview of the MTVTX2804AG CPU Interface
2.3 Register Configuration, Frame Transmission, and Frame Reception
The MVTX2804 has many programmable parameters, covering such functions as QoS weights, VLAN control.
In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters
are contained in 8-bit configuration registers. The MVTX2804 allows indirect access to these registers, as
follows:
Two “index” registers (addresses 000 and 001) need to be written, to indicate the desired 16-bit register
address.
To indirectly configure the register addressed by the two index registers, a “configure data” register
(address 010) must be written with the desired 8-bit data.
Similarly, to read the value in the register addressed by the two index registers, the “configure data” register
can now simply be read.
In summary, access to the many internal registers is carried out simply by directly accessing only three registers –
two registers to indicate the address of the desired parameter, and one register to read or write a value. Of course,
CPU Frame
Receiver
FIFO
I/O MUX
Index Reg 1
(Addr = 001)
Index Reg 0
(Addr = 000)
Response Reg
(RO)
(Addr = 111)
Config
Data Reg
(Addr = 010)
(Addr = 011)
8/16-bit
Data Bus
Command/
Status Reg
(Addr = 100)
Interrupt Reg
(Addr = 101)
Control Frame
Data Reg
(Addr = 110)
Data
Reg
CPU Frame
CPU Frame
Transmit
FIFO
Internal
Registers
Synchronous
Serial
Interface
16-bit Address
Interrupt
8/16-bit Data Bus
Frame
Recent
FIFO
Frame
Transmit
FIFO1
Frame
Transmit
FIFO2
8-bit
3-bit Addr
8/16-bit Data Bus
Process
MUX
Search
Engine
Q0
Q1
RD_CYC, WR_CYC
To Rate Control RAM
Statistic Counter RAM
FCB RAM
MCT RAM
External SRAM
VLAN Index
CPU Interface
Data Bus
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