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參數(shù)資料
| 型號： | MX10FMAXDQC |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MS-016A, LCC-44 |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 466K |
| 代理商： | MX10FMAXDQC |
19
MX10FMAXDQC
Specifications subject to change without notice, contact your sales representatives for the most update information.
MX10FMAXDPC
REV. 1.1, MAR. 29, 2005
AC CHARACTERISTICS
(Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and PSEN = 100 pF, Load Capacitance for All
Other Outputs = 80 pF)
tCK min. = 1/f max. (maximum operating frequency); tCK=clock period
SYMBOL
PARAMETER
33 MHz
UNIT
MIN
MAX
EXTERNAL PROGRAM MEMORY
TLHLL
ALE PULSE DURATION
20
-
NS
TAVLL
ADDRESS SET-UP TIME TO ALE
17
-
NS
TLLAX
ADDRESS HOLD TIME AFTER ALE
10
-
NS
TLLIV
TIME FROM ALE TO VALID INSTRUCTION INPUT
-
55
NS
TLLPL
TIME FROM ALE TO CONTROL PULSE PSEN
17
-
NS
TPLPH
CONTROL PULSE DURATION PSEN
70
-
NS
TPLIV
TIME FROM PSEN TO VALID INSTRUCTION INPUT
-
12
NS
TPXIX
INPUT INSTRUCTION HOLD TIME AFTER PSEN
0
-
NS
TPXIZ
INPUT INSTRUCTION FLOAT DELAY AFTER PSEN
-
20
NS
TAVIV
ADDRESS TO VALID INSTRUCTION INPUT
-
95
NS
TPLAZ
TO PSEN ADDRESS FLOAT TIME
-
10
NS
EXTERNAL DATA MEMORY
TLHLL
ALE PULSE DURATION
20
-
NS
TAVLL
ADDRESS SET-UP TIME TO ALE
17
-
NS
TLLAX
ADDRESS HOLD TIME AFTER ALE
10
-
NS
TRLRH
RD PULSE DURATION
80
-
NS
TWLWH
WR PULSE DURATION
80
-
NS
TRLDV
RD TO VALID DATA INPUT
-
60
NS
TRHDX
DATA HOLD TIME AFTER RD
0
-
NS
TRHDZ
DATA FLOAT DELAY AFTER RD
32
-
NS
TLLDV
TIME FROM ALE TO VALID DATA INPUT
-
90
NS
TAVDV
ADDRESS TO VALID INPUT
-
105
NS
TLLWL
TIME FROM ALE TO RD OR WR
40
140
NS
TAVWL
TIME FROM ADDRESS TO RD OR WR
45
-
NS
TWHLH
TIME FROM RD OR WR HIGH TO ALE HIGH
10
55
NS
TQVWX
DATA VALID TO WR TRANSITION
10
-
NS
TQVWH
DATA SET-UP TIME BEFORE WR
125
-
NS
TWHQX
DATA HOLD TIME AFTER WR
10
-
NS
TRLAZ
ADDRESS FLOAT DELAY AFTER RD
-
0
NS
NOTE:
1. The maximun operating frequency is limited to 40 MHz and the minimum to 3.5 MHz.
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