參數(shù)資料
型號： MX7705EUE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC
中文描述： 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： TSSOP-16
文件頁數(shù)： 28/34頁
文件大?。?/td> 664K
代理商： MX7705EUE
M
Using FSYNC
When FSYNC = 1, the digital filter and analog modula-
tor are in a reset state, inhibiting normal operation. Set
FSYNC = 0 to begin calibration or conversion.
When configured for normal operation (MD0 and MD1
set to 0),
DRDY
goes low 3 x 1/output data rate after
FSYNC goes low to indicate that the new conversion
result is ready to be read from the data register.
DRDY
returns high when a read operation on the data register
is complete. As long as FSYNC remains low, the
MX7705 performs free-running conversions with the
data registers updating at the output data rate. If the
valid data is not read before the next conversion result
is ready,
DRDY
returns high for 500 x 1/f
CLKIN
before
going low again to indicate a new conversion. Set
FSYNC = 1 to stop converting data.
If FSYNC goes high while
DRDY
is low (indicating that
valid data has not yet been read from the data regis-
ter),
DRDY
does not reset high.
DRDY
remains low until
the new data is read from the data register or until
FSYNC goes low to begin a new conversion.
Table 15 provides the duration-to-mode bits and dura-
tion-to-
DRDY
for each calibration sequence. Duration-to-
mode bits provide the time required for the calibration
sequence to complete (MD1 and MD0 return to 0).
Duration-to-
DRDY
provides the time until the first conver-
sion result is valid in the data register (
DRDY
goes low).
The pipeline delay necessary to ensure that the first
conversion result is valid is t
P
(t
P
= 2000 x 1/f
CLKIN
).
When selecting self-calibration (MD1 = 0, MD0 = 1),
DRDY
goes low 9 x 1/output data rate + t
P
after FSYNC
goes low (or after a write operation to the setup register
with MD1 = 0 and MD0 = 1 is performed while FSYNC
is already low) to indicate new data in the data register.
The pipeline delay required to ensure that the first con-
version result is valid is t
P
(t
P
= 2000 x 1/f
CLKIN
).
When zero-scale or full-scale calibration is selected,
DRDY
goes low 4 x 1/output data rate + t
P
after FSYNC
goes low (or while the zero-scale or full-scale calibra-
tion command is issued when FSYNC is already low) to
indicate new data in the data register (see the
Calibration
section).
Calibration
To compensate for errors introduced by temperature
variations or system DC offsets, perform an on-chip cal-
ibration. Select calibration options by writing to the
MD1 and MD0 bits in the setup register (Table 9).
Calibration removes gain and offset errors from the
device and/or the system. Recalibrate with changes in
ambient temperature, supply voltage, bipolar/unipolar
mode, PGA gain, and output data rate.
The MX7705 offers two calibration modes, self-calibra-
tion and system calibration. The channels of the
MX7705 are independently calibrated (Table 8). The
calibration coefficients resulting from a calibration
sequence on a selected channel are stored in the corre-
sponding offset and gain-register pair.
Self- and system calibration automatically calculate the
offset and gain coefficients, which are written to the off-
set and gain registers. These offset and gain coeffi-
cients provide offset and gain-error correction for the
specified channel.
Self-Calibration
Self-calibration compensates for offset and gain errors
internal to the ADC. Prior to calibration, set the PGA gain,
unipolar/bipolar mode, and input channel setting. During
self-calibration, AIN+ and AIN- of the selected channel
are internally shorted together. The ADC calibrates this
condition as the zero-scale output level. For bipolar
mode, this zero-scale point is the midscale of the bipolar
transfer function.
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
28
______________________________________________________________________________________
Table 15. Calibration Sequences
CALIBRATION TYPE
(MD1, MD0)
CALIBRATION SEQUENCE
DURATION-TO-MODE
BITS*
DURATION TO
DRDY
**
Self-calibration (0,1)
Internal zero-scale calibration at
selected gain + internal full-scale
calibration at selected gain
6 x 1/output data rate
9 x 1/output data rate + t
P
Zero-scale system calibration (1,0)
Zero-scale calibration on AIN at
selected gain
3 x 1/output data rate
4 x 1/output data rate + t
P
Full-scale system calibration (1,1)
Full-scale calibration on AIN at
selected gain
3 x 1/output data rate
4 x 1/output data rate + t
P
*
Duration-to-mode bits represents the completion of the calibration sequence.
**
Duration to
DRDY
represents the time at which a new conversion result is available in the data register.
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參數(shù)描述
MX7705EUE+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MX7705EUE+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MX7705EUE-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MX7705EWE 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MX7705EWE+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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