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參數(shù)資料
| 型號： | MXD1000SA__ |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 5-Tap Silicon Delay Line |
| 中文描述： | 5抽頭硅延遲線 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 79K |
| 代理商： | MXD1000SA__ |
M
5-Tap S ilic on Delay Line
4
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
1
2
3
4
5
6
7
8
1
4
6
7
8
Signal Input
40% of specified maximum delay
80% of specified maximum delay
Device Ground
100% of maximum specified delay
60% of specified maximum delay
20% of specified maximum delay
Power-Supply Input
14-PIN DIP
FUNCTION
8-PIN
DIP/SO/μMAX
NAME
16-PIN SO
4
6
1
IN
TAP2
TAP4
GND
TAP5
TAP3
TAP1
V
CC
PIN
8
9
10
12
14
11
13
16
—
2, 3, 5, 9, 11,
13
No Connection. Not internally connected.
2, 3, 5, 7, 10,
12, 14, 15
N.C.
Note:
Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.
_______________Definitions of Terms
Period:
The time elapsed between the first pulse’s
leading edge and the following pulse’s leading edge.
Pulse Width (t
WI
):
The time elapsed on the pulse
between the 1.5V level on the leading edge and the
1.5V level on the trailing edge, or vice-versa.
Input Rise Time (t
RISE
):
The time elapsed between
the 20% and 80% points on the input pulse’s leading
edge.
Input Fall Time (t
FALL
):
The time elapsed between
the 80% and 20% points on the input pulse’s trailing
edge.
Time Delay, Rising (t
PLH
):
The time elapsed between
the 1.5V level on the input pulse’s leading edge and the
corresponding output pulse’s leading edge.
Time Delay, Falling (t
PHL
):
The time elapsed between
the 1.5V level on the input pulse’s trailing edge and the
corresponding output pulse’s trailing edge.
____________________Test Conditions
Ambient Temperature:
+25°C ±3°C
Supply Voltage (V
CC
):
+5V ±0.1V
Input Pulse:
High = 3.0V ±0.1V
Low = 0.0V ±0.1V
Source Impedance:
50
max
Rise and Fall Times:
3.0ns max
Pulse Width:
500ns max (1ns for -500)
Period:
1μs (2ns for -500)
Each output is loaded with a 74F04 input gate. Delay is
measured at the 1.5V level on the rising and falling
edges. The time delay due to the 74F04 is subtracted
from the measured delay.
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PDF描述 |
|---|---|
| MXD1000UA__ | 5-Tap Silicon Delay Line |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MXD1000SA__ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:5-Tap Silicon Delay Line |
| MXD1000SA050 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MXD1000SA075-T | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| MXD1000SA100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| MXD1000SA125 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
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