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參數(shù)資料
| 型號(hào)： | MXD1005SE75 |
| 廠(chǎng)商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類(lèi)： | 延遲線(xiàn) |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | MXD1005SE75 |
__________Applications Information
Supply and Temperature
Effects on Delay
Variations in supply voltage may affect the MXD1005’s
fixed tap delays. Supply voltages beyond the specified
range may result with larger variations. The devices are
internally compensated to reduce the effects of temper-
ature variations. Although these devices might vary with
supply and temperature, the delays vary unilaterally,
which suggests that TAP3 can never be faster than
TAP2.
Capacitance and Loading
Effects on Delay
The output load can affect the tap delays. Larger
capacitances tend to lengthen the rising and falling
edges, thus increasing the tap delays. As the taps are
loaded with other logic devices, the increased load will
increase the tap delays.
Board Layout Considerations/Decoupling
The device should be driven with a source that can
deliver the required current for proper operation. A
0.1F ceramic bypassing capacitor could be used. The
board should be designed to reduce stray capaci-
tance.
MXD1005
5-Tap Silicon Delay Line
_______________________________________________________________________________________
5
VIL
VIH
PERIOD
tRISE
IN
OUT
0.6V
2.4V
1.5V
tFALL
tWI
tPLH
tPHL
20%
50
0.1F
VCC
IN
(+5V)
20%
TIME
MEASUREMENT
UNIT
TAP1
TAP2
TAP3
TAP4
TAP5
74FO4
20%
MXD1005
Figure 1. Timing Diagram
Figure 2. Test Circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MXD1005UA__ | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:5-Tap Silicon Delay Line |
| MXD1005UA100 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Tapped Delay Line |
| MXD1005UA125 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Tapped Delay Line |
| MXD1005UA150 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Tapped Delay Line |
| MXD1005UA175 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Tapped Delay Line |
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