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參數(shù)資料
| 型號： | MXD1005UA75 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 延遲線 |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO8 |
| 封裝： | UMAX-8 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 89K |
| 代理商： | MXD1005UA75 |
_______________Definitions of Terms
Period: The time elapsed between the first pulse’s
leading edge and the following pulse’s leading edge.
Pulse Width (tWI): The time elapsed on the pulse
between the 1.5V level on the leading edge and the
1.5V level on the trailing edge, or vice-versa.
Input Rise Time (tRISE): The time elapsed between
the 20% and 80% points on the input pulse’s leading
edge.
Input Fall Time (tFALL): The time elapsed between
the 80% and 20% points on the input pulse’s trailing
edge.
Time Delay, Rising (tPLH): The time elapsed between
the 1.5V level on the input pulse’s leading edge and the
corresponding output pulse’s leading edge.
Time Delay, Falling (tPHL): The time elapsed between
the 1.5V level on the input pulse’s trailing edge and the
corresponding output pulse’s trailing edge.
____________________Test Conditions
Ambient Temperature:
+25°C ±3°C
Supply Voltage (VCC):
+5V ±0.01V
Input Pulse:
High = 3.0V ±0.1V
Low = 0.0V ±0.1V
Source Impedance:
50
max
Rise and Fall Times:
3.0ns max
Pulse Width:
500ns max
Period:
1s
Each output is loaded with a 74F04 input gate. Delay is
measured at the 1.5V level on the rising and falling
edges. The time delay due to the 74F04 is subtracted
from the measured delay.
MXD1005
5-Tap Silicon Delay Line
4
_______________________________________________________________________________________
______________________________________________________________Pin Description
1
Signal Input
14-PIN DIP
FUNCTION
8-PIN
DIP/SO/MAX
NAME
16-PIN SO
2
4
40% of specified maximum delay
4
1
IN
TAP2
3
PIN
6
80% of specified maximum delay
4
7
Device Ground
8
6
TAP4
GND
5
8
100% of maximum specified delay
6
10
60% of specified maximum delay
11
9
TAP5
TAP3
7
12
20% of specified maximum delay
8
14
Power-Supply Input
16
13
TAP1
VCC
—
2, 3, 5, 9, 11,
13
No Connection. Not internally connected.
2, 3, 5, 7, 10,
12, 14, 15
N.C.
Note: Maximum delay is determined by the part number extension. See the Part Number and Delay Times table for more information.
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| MXD1013-100CPA | SILICON DELAY LINE, TRUE OUTPUT, PDIP8 |
| MXD1013-40CPA | SILICON DELAY LINE, TRUE OUTPUT, PDIP8 |
| MXD1013-45ESA | SILICON DELAY LINE, TRUE OUTPUT, PDSO8 |
| MXD1013-25C/D | SILICON DELAY LINE, TRUE OUTPUT, UUC16 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MXD1013 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-in-1 Silicon Delay Line |
| MXD1013-12CPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| MXD1013-12CPD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| MXD1013-12CSA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| MXD1013-12CWE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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