參數(shù)資料
型號(hào): MXL1016CS8+C60349
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/5頁(yè)
文件大?。?/td> 0K
描述: IC COMPARATOR TTL 8SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 帶鎖銷(xiāo)
元件數(shù): 1
輸出類(lèi)型: 補(bǔ)充型,TTL
電壓 - 電源,單路/雙路(±): 5 V ~ 10 V,±2.5 V ~ 5 V
電壓 - 輸入偏移(最小值): 3mV @ ±5V
電流 - 輸入偏壓(最小值): 10µA @ ±5V
電流 - 輸出(標(biāo)準(zhǔn)): 20mA
電流 - 靜態(tài)(最大值): 35mA
CMRR, PSRR(標(biāo)準(zhǔn)): 96dB CMRR,100dB PSRR
傳輸延遲(最大): 14ns
工作溫度: 0°C ~ 70°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
安裝類(lèi)型: 表面貼裝
包裝: 管件
MXL1016
Ultra-Fast Precision TTL Comparator
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 5V, V- = -5V, VOUT(Q) = 1.4V, VLE = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Latch Pin High Input Voltage
VIH
2.0
V
Latch Pin Low Input Voltage
VIL
0.8
V
Latch Pin Current
IIL
VLE = 0V
-500
A
TA = +25°C10
14
VIN = 100mV,
OD = 5mV
16
TA = +25°C9
12
Propagation Delay (Note 5)
tPD
VIN = 100mV,
OD = 20mV
15
ns
Differential Propagation Delay
(Note 5)
tPD
VIN = 100mV, OD = 5mV, TA = +25°C4
ns
Latch Setup Time
tSU
(Note 6)
2
ns
Latch Hold Time
tH
(Note 6)
2
ns
Note 1: All specifications are 100% tested at TA = +25°C, unless otherwise noted. Specification limits over temperature (TA = TMIN
to TMAX) are guaranteed by design.
Note 2: Input offset voltage is defined as the average of the two input offset voltages, measured by forcing first one output, then the
other to 1.4V. Input offset current is defined in the same way.
Note 3: Input bias current (IB) is defined as the average of the two input currents.
Note 4: Supply currents are measured with VOUT (Q) driven to both VOH and VOL (not 1.4V).
Note 5: tPD and
tPD cannot be measured in automatic handling equipment with low values of overdrive. Characterization and
correlation tests have shown that tPD and
tPD limits can be guaranteed by design. Electrical Characteristic DC tests are
performed to guarantee that all internal bias conditions are correct. For low overdrive conditions, VOS is added to overdrive.
Note 6: Input latch setup time, tSU, is the interval in which the input signal must be stable prior to asserting the latch signal. The hold
time, tH, is the interval after the latch is asserted in which the input signal must be stable.
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