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參數(shù)資料
| 型號： | N74F193D,602 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 0K |
| 描述： | IC BINARY COUNTER UP/DOWN 16SOIC |
| 標準包裝： | 1,000 |
| 系列： | 74F |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上，下 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 4 |
| 復位： | 異步 |
| 計數(shù)速率： | 125MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設(shè)備封裝： | 16-SO |
| 包裝： | 管件 |
| 其它名稱： | 933888910602 N74F193D N74F193D-ND |
Philips Semiconductors
Product specification
74F193
Up/down binary counter with separate up/down clocks
2
1995 Jul 17
853-0353 15459
FEATURES
Synchronous reversible 4-bit counting
Asynchronous parallel load capability
Asynchronous reset (clear)
Cascadable without external logic
DESCRIPTION
The 74F193 is a 4-bit synchronous up/down counter in the binary
mode. Separate up/down clocks, CPU and CPD respectively,
simplify operation. The outputs change state synchronously with the
Low-to-High transition of either clock input. If the CPU clock is
pulsed while CPD is held High, the device will count up. If CPD clock
is pulsed while CPU is held High, the device will count down. The
device can be cleared at any time by the asynchronous reset pin. It
may also be loaded in parallel by activating the asynchronous
parallel load pin.
Inside the device are four master-slave JK flip-flops with the
necessary steering logic to provide the asynchronous reset,
asynchronous preset, load, and synchronous count up and count
down functions.
Each flip-flop contains JK feedback from slave to master, such that a
Low-to-High transition on the CPD input will decrease the count by
one, while a similar transition on the CPU input will advance the
count by one.
One clock should be held High while counting with the other,
because the circuit will either count by twos or not at all, depending
on the state of the first JK flip-flop, which cannot toggle as long as
either clock input is Low. Applications requiring reversible operation
must make the reversing decision while the activating clock is High
to avoid erroneous counts.
The Terminal Count Up (TCU) and Terminal Count Down (TCD)
outputs are normally High. When the circuit has reached the
maximum count state of 15, the next High-to-Low transition of CPU
will cause TCU to go Low. TCU will stay Low until CPU goes High
again, duplicating the count up clock, although delayed by two gate
delays. Likewise, the TCD output will go Low when the circuit is in
the zero state and the CPD goes Low. The TC outputs can be used
as the clock input signals to the next higher order circuit in a
multistage counter, since they duplicate the clock waveforms.
Multistage counters will not be fully synchronous since there is a
two-gate delay time difference added for each stage that is added.
The counter may be preset by the asynchronous parallel load
capability of the circuit. Information present on the parallel Data
inputs (D0 - D3) is loaded into the counter and appears on the
outputs regardless of the conditions of the clock inputs when the
Parallel Load (PL) input is Low. A High level on the Master Reset
(MR) input will disable the parallel load gates, override both clock
inputs, and set all Q outputs Low. If one of the clock inputs is Low
during and after a reset or load operation, the next Low-to-High
transition of the clock will be interpreted as a legitimate signal and
will be counted.
TYPE
TYPICAL fMAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F193
125MHz
32mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
16-pin plastic DIP
N74F193N
SOT38-4
16-pin plastic SO
N74F193D
SOT109-1
PIN CONFIGURATION
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D1
Q1
Q0
CPD
CPU
Q2
Q3
D0
TCD
TCU
D2
D3
PL
GND
MR
VCC
SF00745
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D3
Data inputs
1.0/1.0
20
A/0.6mA
CPU
Count up clock input (active rising edge)
1.0/3.0
20
A/1.8mA
CPD
Count down clock input (active rising edge)
1.0/3.0
20
A/1.8mA
PL
Asynchronous parallel load control input (active Low)
1.0/1.0
20
A/0.6mA
MR
Asynchronous master reset input
1.0/1.0
20
A/0.6mA
Q0 - Q3
Flip-flop outputs
50/33
1.0mA/20mA
TCU
Terminal count up (carry) output (active Low)
50/33
1.0mA/20mA
TCD
Terminal count down (borrow) output (active Low)
50/33
1.0mA/20mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20
A in the High state and 0.6mA in the Low state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| N74F193D-T | 功能描述:計數(shù)器 IC 4-BIT BIN U/D COUNTR RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| N74F193N | 功能描述:計數(shù)器 IC 4-BIT BIN U/D COUNTR RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| N74F193N,602 | 功能描述:計數(shù)器 IC 4-BIT BIN U/D COUNTR RoHS:否 制造商:NXP Semiconductors 計數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計數(shù)法: 計數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| N74F194D | 功能描述:計數(shù)器移位寄存器 4-BIT SHIFT REGISTER RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| N74F194D,602 | 功能描述:計數(shù)器移位寄存器 4-BIT SHIFT REGISTER RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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