NB100LVEP17
http://onsemi.com
2
D1
D2
Q0
Q1
VEE
D0
Q0
D2
D0
D3
VCC
Figure 1. Logic Diagram
Q2
Q3
Q2
VBB
R1
R2
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default
State
Description
TSSOP
QFN
1,20
13,18,21,
22,23
VCC
Positive Supply Voltage. All VCC Pins Must be Externally Connected
to Power Supply to Guarantee Proper Operation.
11
10
VEE
Negative Supply Voltage. All VEE Pins Must be Externally Con-
nected to Power Supply to Guarantee Proper Operation.
10
9
VBB
ECL Reference Voltage Output.
2,4,6,8
1,3,5,7
D[0:3]
ECL Input
Low
Noninverted Differential Inputs [0:3]. Internal 75 kW to VEE.
3,5,7,9
2,4,6,8
D[0:3]
ECL Input
High
Inverted Differential Inputs [0:3]. Internal 75 kW to VEE and 37 kW to
VCC.
19,17,15,13
12,15,17,2
0
Q[0:3]
ECL Output
Noninverted Differential Outputs [0:3]. Typically Terminated with
50 W to VTT = VCC 2 V.
18,16,14,12
11,14,16,1
9
Q[0:3]
ECL Output
Inverted Differential Outputs [0:3]. Typically Terminated with 50 W to
VTT = VCC 2 V.
N/A
24
NC
No Connect. The NC Pin is Electrically Connected to the Die and
“MUST BE” Left Open.
N/A
EP
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad
on the package bottom (see case drawing) must be attached to a heatsinking conduit.