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參數(shù)資料
| 型號： | NB4L16MMNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER DVR TRANSLA 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 緩沖器/驅(qū)動器，變換器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，HSTL，LVCMOS，LVDS，LVPECL，LVTTL |
| 輸出： | CML |
| 頻率 - 最大： | 3.5GHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 3
1
Publication Order Number:
NB4L16M/D
NB4L16M
2.5V/3.3V, 5 Gb/s Multi Level
Clock/Data Input to CML
Driver / Receiver / Buffer/
Translator with Internal
Termination
Description
The NB4L16M is a differential driver/receiver/buffer/translator
which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL
and produce 400 mV CML output. The device is capable of receiving,
buffering, and translating a clock or data signal that is as small as
75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is
ideal for SONET, GigE, Fiber Channel and backplane applications
Differential inputs incorporate internal 50
W termination resistors
and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL
or LVDS. The differential 16 mA CML output provides matching
internal 50
W termination, and 400 mV output swing when externally
receiver terminated, 50
provide transmission line termination on chip, at the receiver and
driver end, eliminating any use of additional external components.
The VBB, an internally generated voltage supply, is available to this
device only. For singleended input configuration, the unused
complementary differential input is connected to VBB as a switching
reference voltage. The VBB reference output can be used also to
rebias capacitor coupled differential or singleended output signals.
For the capacitor coupled input signals, VBB should be connected to
the VTD pin and bypassed to ground with a 0.01 mF capacitor. When
not used VBB should be left open.
This device is housed in a 3x3 mm 16 pin QFN package.
Application notes, models, and support documentation are available at
Features
Maximum Input Clock Frequency up to 3.5 GHz
Maximum Input Data Rate up to 5.0 Gb/s
< 0.7 ps Maximum Clock RMS Jitter
< 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s
220 ps Typical Propagation Delay
60 ps Typical Rise and Fall Times
CML Output with Operating Range:
VCC = 2.375 V to 3.6 V with VEE = 0 V
CML Output Level (400 mV PeaktoPeak Output),
Differential Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
16
NB4L
16M
ALYWG
G
1
Q
Figure 1. Functional Block Diagram
VTD
D
50 W
VTD
50 W
R1
R2
R1
R2
VEE
VCC
(Note: Microdot may be in either location)
1
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