- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄8464 > NB4L52MNG (ON Semiconductor)IC FLIP FLOP DATA/CLK DFF 16-QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | NB4L52MNG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP DATA/CLK DFF 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 123 |
| 功能： | 復(fù)位 |
| 類(lèi)型： | D 型 |
| 輸出類(lèi)型： | 差分 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 1 |
| 延遲時(shí)間 - 傳輸： | 400ps |
| 觸發(fā)器類(lèi)型： | 負(fù)邊沿 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤(pán) |
| 包裝： | 管件 |
| 其它名稱(chēng)： | NB4L52MNG-ND NB4L52MNGOS |
Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 3
1
Publication Order Number:
NB4L52/D
NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip-Flop
with Reset
MultiLevel Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flipflop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50
W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
Maximum Input Clock Frequency > 4 GHz Typical
330 ps Typical Propagation Delay
145 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
Internal Input Termination Resistors, 50 W
Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
MARKING DIAGRAM*
http://onsemi.com
QFN16
MN SUFFIX
CASE 485G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
16
NB4L
52
ALYWG
G
1
Data
Clock
Reset
VTD
VTCLK
D
CLK
VTR R
R
D
CLK
Q
Hx
x
L
LL
Z
L
LH
Z
H
Z = LOW to HIGH Transition
x = Don’t Care
Table 1. TRUTH TABLE
Figure 1. Logic Diagram
D
VTD
CLK
VTCLK
VTR
R
Q
(Note: Microdot may be in either location)
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC10EP31DG | IC FLIP FLOP ECL SET/RESET 8SOIC |
| M85049/84-12N03 | BACKSHELL BANDING 90 DEG SIZE 12 |
| M85049/85-14W01 | BACKSHELL BANDING SZ 14 CADMIUM |
| M85049/1825W09B | BACKSHELL EMI RFI SZ 25 CADMIUM |
| M85049/8-49W | BACKSHELL EMI RFI 90 DEG SIZE 10 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB4L52MNR2G | 功能描述:轉(zhuǎn)換 - 電壓電平 ANA ECL D FF W/DIFF RESET RoHS:否 制造商:Micrel 類(lèi)型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時(shí)間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| NB4L6254 | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer |
| NB4L6254D | 制造商:ONSEMI 制造商全稱(chēng):ON Semiconductor 功能描述:2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer |
| NB4L6254FAG | 功能描述:模擬和數(shù)字交叉點(diǎn) IC LVPECL 2X2 SW FANOUT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| NB4L6254FAR2G | 功能描述:模擬和數(shù)字交叉點(diǎn) IC AIT LVPECL 2X2 SW FN RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。