Figure 3. NB6L14S Pinout, 16pin QFN (Top View) Q3 V" />
參數(shù)資料
型號(hào): NB6L14SMNG
廠商: ON Semiconductor
文件頁(yè)數(shù): 4/11頁(yè)
文件大小: 0K
描述: IC CLK BUFFER TRANSLA 1:4 16-QFN
標(biāo)準(zhǔn)包裝: 123
系列: AnyLevel™
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,HSCL,LVDS,LVPECL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
其它名稱: NB6L14SMNG-ND
NB6L14SMNGOS
NB6L14S
http://onsemi.com
2
Figure 3. NB6L14S Pinout, 16pin QFN (Top View)
Q3
VCC
EN
GND
IN
VT
VREFAC
IN
Q1
Q2
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB6L14S
Exposed Pad (EP)
Q0
VCC
IN
EN
Q
01
1
0
10
1
x
0
0 (Note 1)
1. On next transition of the input signal (IN).
Table 1. TRUTH TABLE
Q
1
0
1 (Note 1)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2
Q1
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3
Q2
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4
Q2
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
Q3
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
6
Q3
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
7
VCC
Positive Supply Voltage.
8
EN
LVTTL / LVCMOS Input
Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb
outputs will go HIGH on the next negative transition of IN input. The internal
DFF register is clocked on the falling edge of IN input; see Figure 26. The EN
pin has an internal pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, LVDS
Inverted Differential Input
10
VREFAC
LVPECL Output
The VREFAC reference output can only be used to rebias capacitorcoupled
differential or singleended input signals. For the capacitorcoupled IN and/or
INb inputs, VREFAC should be connected to the VT pin and bypassed to ground
with a 0.01 mF capacitor.
11
VT
LVPECL Output
Internal 100 W Centertapped Termination Pin for IN and IN
12
IN
LVPECL, CML, LVDS
Noninverted Differential Input. (Note 2)
13
GND
Negative Supply Voltage.
14
VCC
Positive Supply Voltage.
15
Q0
LVDS Output
Noninverted IN output. Typically loaded with 100 W receiver termination
resistor across differential pair.
16
Q0
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor
across differential pair.
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heatsinking conduit. The pad is not electrically connected to the
die, but is recommended to be electrically and thermally connected to GND on
the PC board.
2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied
on IN/IN inputs, then the device will be susceptible to selfoscillation.
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