- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16726 > NB6L295MNGEVB (ON Semiconductor)BOARD EVAL NB6L295MN CLK DELAY PDF資料下載
參數(shù)資料
| 型號： | NB6L295MNGEVB |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL NB6L295MN CLK DELAY |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘分配 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | NB6L295 |
| 次要屬性： | SMA 連接器 |
| 已供物品： | 板 |
| 其它名稱： | NB6L295MNGEVB-ND NB6L295MNGEVBOS |
NB6L295
http://onsemi.com
8
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL
PSEL
Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
01
PD1 Latch
PD0 Latch
PD0 Delay
PD1 Delay
SLOAD
Q1/Q1
Q0/Q0
SDATA
SCLK
11Bit Shift Register
MSEL
Serial Data Interface Loading
Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by
using the SCLK input pin and latching the data with the SLOAD input pin. The 11bit SHIFT REGISTER shifts once per rising
edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section
of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOWtoHIGH edge
transition (transparent state) into a data Latch register and latches the data with a subsequent HIGHtoLOW edge transition.
Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL
and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence.
Input EN should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After
programming, the EN should be returned LOW (enabled) for functional delay operation.
The disabling of EN (HIGH) forces Qx LOW and Qx HIGH and is included during programming to prevent (or mask out)
any potential runt pulses or extended pulses which might occur in the internal delay gates programming switching, but it is not
required for programming.
SDIN
SCLK
SLOAD
LSB
EN
MSB
PSEL MSEL
D0
D1
D2
D3
D4
D5
D6
D7
D8
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
Figure 8. SDI Timing Diagram
ts SDIN to
SCLK
th SDIN to SCLK
ts SCLK to SLOAD
tpwmin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GBC15DREF-S13 | CONN EDGECARD 30POS .100 EXTEND |
| R-551.8DA | CONV DC/DC 5A 4.5-18VIN 1.8V |
| ECM25DCMT | CONN EDGECARD 50POS .156 WW |
| REC5-243.3DRW/H6/C | CONV DC/DC 5W 18-36VIN +/-3.3V |
| EBA22DRMT | CONN EDGECARD 44POS .125 SQ WW |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB6L295MNTXG | 功能描述:延遲線/計時元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| NB6L56MNG | 功能描述:時鐘緩沖器 TSMC 2.5V/3.3V DUAL DIFF RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| NB6L56MNTXG | 功能描述:時鐘緩沖器 2.5V/3.3V DUAL DIFFERENTI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| NB6L572M | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator |
| NB6L572MMNG | 功能描述:編碼器、解碼器、復用器和解復用器 ANA 500MA ANY CAP LDO RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。