VEE Q3 Q3 VCC<" />
參數(shù)資料
型號(hào): NB7L14MMNEVB
廠商: ON Semiconductor
文件頁(yè)數(shù): 4/11頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR NB7L14MMN
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘緩沖器 / 驅(qū)動(dòng)器 / 接收器 / 變換器
嵌入式:
已用 IC / 零件: NB7L14M
主要屬性: 輸入最高達(dá) 12Gb/s 和 8GHz
次要屬性: 差分式 CML 輸出
已供物品:
其它名稱: NB7L14MMNEVBOS
NB7L14M
http://onsemi.com
2
VEE Q3
Q3 VCC
VEE Q0
Q0
VCC
Q1
Q2
VTCLK
CLK
VTCLK
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L14M
Exposed Pad (EP)
Figure 2. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
Internal 50 W Termination Pin for CLK.
2
CLK
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Inverted Differential Clock/Data Input. (Note 1)
3
CLK
LVPECL, CML,
LVCMOS, LVTTL,
LVDS
Noninverted Differential Clock/Data Input. (Note 1)
4
VTCLK
Internal 50 W Termination Pin for CLK.
5,16
VEE
Power Supply
Negative Supply Voltage. All VEE pins must be externally connected to a Power Supply to
guarantee proper operation.
6
Q3
CML Output
Inverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2)
7
Q3
CML Output
Noninverted Differential Output 3 with Internal 50 W Source Termination Resistor. (Note 2)
8,13
VCC
Power Supply
Positive Supply Voltage. All VCC pins must be externally connected to a Power Supply to
guarantee proper operation.
9
Q2
CML Output
Inverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2)
10
Q2
CML Output
Noninverted Differential Output 2 with Internal 50 W Source Termination Resistor. (Note 2)
11
Q1
CML Output
Inverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2)
12
Q1
CML Output
Noninverted Differential Output 1 with Internal 50 W Source Termination Resistor. (Note 2)
14
Q0
CML Output
Inverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2)
15
Q0
CML Output
Noninverted Differential Output 0 with Internal 50 W Source Termination Resistor. (Note 2)
EP
Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking
conduit to improve heat transfer. It is recommended to connect the EP to the lower
potential (VEE).
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK, then the device will be susceptible to selfoscillation.
2. CML outputs require 50 W receiver termination resistors to VCC for proper operation.
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