NB7L216
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2
VEE
VEE VBB VEE VEE
VCC
Q
VCC
VTD
D
VTD
56
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L216
Exposed Pad (EP)
Figure 3. QFN16 Pinout (Top View)
VEE VEE VEE
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTD
Internal 50 W termination pin. See Table
7. Note
12
D
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted differential input. Note
1.3
D
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted differential input. Note
1.4
VTD
Internal 50 W termination pin. See Table
7. Note
1.15
VBB
Internally generated ECL reference voltage supply.
5, 6, 7, 8, 13, 14, 16
VEE
Negative supply voltage. All VEE pins must be externally connected to power
supply to guarantee proper operation.
9, 12
VCC
Positive supply voltage. All VCC pins must be externally connected to power
supply to guarantee proper operation
10
Q
RSECL Output
Noninverted differential output. Typically receiver terminated with 50 W resistor
to VTT = VCC 2.0 V.
11
Q
RSECL Output
Inverted differential output. Typically receiver terminated with 50 W resistor to
VTT = VCC 2.0 V.
EP
Exposed pad (EP). Thermally exposed pad on the package bottom must be
attached to a heat sinking conduit. It is recommended to connect the EP to the
lower potential, VEE.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage and if no signal
is applied on D/D input then the device will be susceptible to selfoscillation.