Table 6. AC CHARACTERISTICS VCC = 2." />
參數(shù)資料
型號: NB7L585MNR4G
廠商: ON Semiconductor
文件頁數(shù): 5/9頁
文件大?。?/td> 0K
描述: IC CLK/DATA BUFFER MUX 1:6 32QFN
標(biāo)準(zhǔn)包裝: 1,000
系列: GigaComm™
類型: 扇出緩沖器(分配),多路復(fù)用器,數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: LVPECL
頻率 - 最大: 5GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 帶卷 (TR)
NB7L585
http://onsemi.com
5
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = 40°C to 85°C (Note 11)
Symbol
Characteristic
Min
Typ
Max
Unit
fMAX
Maximum Input Clock Frequency; VOUTpp w 400 mV
5
7
GHz
fDATAMAX Maximum Operating Data Rate (PRBS23)
8
10
Gbps
fSEL
Maximum Toggle Frequency, SEL
1.0
1.5
GHz
VOUTpp
Output Voltage Amplitude (@ VINPPmin)
fin ≤ 4 GHz
(Note 12) (Figures 8 and 10)
fin ≤ 5 GHz
550
400
800
650
mV
tPLH,
tPHL
Propagation Delay to Differential Outputs, @ 1 GHz,
measured at differential crosspoint
IN/IN to Q/Q
SEL to Q
125
75
175
200
250
300
ps
tPLH TC
Propagation Delay Temperature Coefficient
50
Dfs/°C
tskew
Output Output skew (within device) (Note 13)
Device Device skew (tpd max – tpdmin)
20
100
ps
tDC
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
fin v 5.0 GHz
45
50
55
%
FN
Phase Noise, fin = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
135
137
149
150
151
dBc
t FN
Integrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset (RMS)
36
fs
tJITTER
RJ – Output Random Jitter (Note 14)
fin ≤ 5.0 GHz
DJ Residual Output Deterministic Jitter (Note 15)
≤ 8 Gbps
0.2
5
0.8
15
ps rms
ps pkpk
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
0.7
psRMS
VINPP
Input Voltage Swing (Differential Configuration) (Note 16)
100
1200
mV
tr,, tf
Output Rise/Fall Times @ 1 GHz (20% 80%), Q, Q
25
55
85
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV pkpk source, 50% duty cycle clock source. All output loading with external 50 W to VCC – 2 V. Input edge
rates 40 ps (20% 80%).
12.Output voltage swing is a singleended measurement operating in differential mode.
13.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23.
16.Input voltage swing is a singleended measurement operating in differential mode.
17.Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Clock Output Voltage Amplitude (VOUTpp) vs. Input Frequency (fin) at Ambient Temperature (Typical)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
0
200
1000
01
8
7
6
5
4
23
Q AMP (mV)
800
600
400
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