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參數(shù)資料
| 型號： | NB7V52MMNTXG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 0K |
| 描述： | IC FLIP FLOP DIFF RST/CML 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | 復(fù)位 |
| 類型： | D 型 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 1 |
| 延遲時間 - 傳輸： | 300ps |
| 觸發(fā)器類型： | 負(fù)邊沿 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
NB7V52M
http://onsemi.com
2
VTCLK CLK CLK VTCLK
VTR
R
VTR
VCC
Q
VEE
VTD
D
VTD
5
678
16
15
14
13
12
11
10
9
1
2
3
4
NB7V52M
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
R
D
CLK
Q
H
x
L
Z
L
H
Z
H
Z = LOW to HIGH Transition
x = Don’t care
Table 1. Pin Description
Pin
Name
I/O
Description
1
VTD
Internal 50 W Termination Pin for D
2
D
LVPECL, CML,
LVDS Input
Noninverted Differential Data Input. (Note 1)
3
D
LVPECL, CML,
LVDS Input
Inverted Differential Data Input. (Note 1)
4
VTD
Internal 50 W Termination Pin for D
5
VTCLK
Internal 50 W Termination Pin for CLK
6
CLK
LVPECL, CML,
LVDS Input
Noninverted Differential Clock Input. (Note 1)
7
CLK
LVPECL, CML,
LVDS Input
Inverted Differential Clock Input. (Note 1)
8
VTCLK
Internal 50 W Termination Pin for CLK
9
VEE
Negative Supply Voltage. (Note 2)
10
Q
CML Output
Inverted Differential Output
11
Q
CML Output
Noninverted Differential Output
12
VCC
Positive Supply Voltage. (Note 2)
13
VTR
Internal 50 W Termination Pin for R
14
R
LVPECL, CML,
LVDS Input
Noninverted Asynchronous Differential Reset Input. (Note 1)
15
R
LVPECL, CML,
LVDS Input
Inverted Asynchronous Differential Reset Input. (Note 1)
16
VTR
Internal 50 W Termination Pin for R
EP
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTx, VTx) are connected to a common termination voltage or left open, and
if no signal is applied on CLK/CLK input, then the device will be susceptible to selfoscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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