參數(shù)資料
型號: NBSG11BAEVB
廠商: ON Semiconductor
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: BOARD EVALUATION BBG NBSG11BA
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘分配
嵌入式:
已用 IC / 零件: NBSG11
已供物品:
其它名稱: NBSG11BAEVB-ND
NBSG11BAEVBOS
Semiconductor Components Industries, LLC, 2011
January, 2011 Rev. 16
1
Publication Order Number:
NBSG11/D
NBSG11
2.5V/3.3VSiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
Description
The NBSG11 is a 1to2 differential fanout buffer, optimized for
low skew and UltraLow JITTER.
Inputs incorporate internal 50
W termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are Reduced Swing ECL (RSECL),
400 mV. All outputs loaded with 50
W to VCC 1.5 V for BGA
package and VCC 2 V for QFN package.
Features
Maximum Input Clock Frequency up to 12 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: VCC = 2.375 V to 3.465 V
with VEE = 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = 2.375 V to 3.465 V
RSECL Output Level (400 mV PeaktoPeak Output), Differential
Output Only
50 W Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
FCBGA16
BA SUFFIX
CASE 489
MARKING DIAGRAMS*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
SG
11
ALYWG
G
16
SG
11
ALYWG
G
1
1
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