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參數(shù)資料
| 型號： | NBSG16MMN |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer |
| 中文描述： | LINE TRANSCEIVER, PQCC16 |
| 封裝： | QFN-16 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 81K |
| 代理商： | NBSG16MMN |
NBSG16M
http://onsemi.com
8
Table 8. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
= 3.465 V to 2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
OUTPP
Output Voltage Amplitude
(See Figure 4) (Note 15)
f
in
< 7 GHz
f
in
< 10 GHz
300
200
400
250
300
200
400
250
300
100
400
150
mV
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90
110
150
100
120
150
100
125
155
ps
t
SKEW
Duty Cycle Skew (Note 16)
3
15
3
15
3
15
ps
t
JITTER
RMS Random Clock Jitter (Note 18)
f
in
< 10 GHz
PeaktoPeak Data Dependent Jitter (Note 19)
f
in
< 10 Gb/s
0.2
8
1
15
0.2
8
1
15
0.2
8
1.0
15
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 17)
75
2500
75
2500
75
2500
mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% 80%)
Q, Q
21
35
53
21
35
53
21
35
53
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
15.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 to V
CC
. Input edge rates 40 ps (20% 80%).
16.See Figure 5 t
= |t
t
PHL
| for a nominal 50% differential clock input waveform.
17.V
cannot exceed V
EE
. (Applicable only when V
CC
V
EE
< 2500 mV). Input voltage swing is a singleended measurement
operating in differential mode.
18.Additive RMS jitter with 50% duty cycle clock signal at 10GHz.
19.Additive PeaktoPeak data dependent jitter with NRZ PRBS2
31
1 data rate at 10 Gb/s.
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) at Ambient Temperature (Typical)
0
50
100
150
200
250
300
350
400
450
500
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
O
V
CC
V
EE
= 3.3 V
V
CC
V
EE
= 2.5 V
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