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參數(shù)資料
型號: NBVSPA018LN1TAG
廠商: ON Semiconductor
文件頁數(shù): 2/8頁
文件大?。?/td> 0K
描述: IC VCXO LVDS 155.52MHZ 6CLCC
標準包裝: 1,000
系列: PureEdge™
類型: VCXO
頻率: 155.52MHz
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 6-CLCC
包裝: 帶卷 (TR)
供應商設備封裝: 6-CLCC(7x5)
安裝類型: 表面貼裝
NBVSPA015 Series
http://onsemi.com
2
Figure 1. Simplified Logic Diagram
PLL
Clock
Multiplier
Crystal
GND
OE
VC
CLK CLK
VDD
65
4
12
3
LVDS
2030
MHz
OE
VC
GND
CLK
VDD
CLK
1
2
3
6
5
4
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
VC (Note 1)
Analog Input
Analog control voltage input pin that adjusts output oscillation frequency. f0 =VC = 1.65 V
2
OE
LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
3
GND
Power Supply
Ground at 0 V. Electrical and Case Ground.
4
CLK
LVDS Output
NonInverted Clock Output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
CLK
LVDS Output
Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across
differential pair.
6
VDD
Power Supply
Positive Power Supply Voltage. Voltage should not exceed 3.3 V ±10%.
1. Control voltage has a positive slope with a typical linearity of ±10%; VC = 1.65 V ± 1 V.
Table 2. OUTPUT ENABLE TRISTATE FUNCTION
OE Pin
Output Pins
Open
Active
HIGH Level
Active
LOW Level
High Z
Table 3. ATTRIBUTES
Characteristic
Value
Input Default State Resistor
170 kW
ESD Protection
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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