參數(shù)資料
型號: NCP1081DEG
廠商: ON Semiconductor
文件頁數(shù): 15/18頁
文件大小: 257K
描述: IC CONV CTLR POE-PD 40W 20-TSSOP
標準包裝: 74
類型: 以太網(wǎng)供電開關(PoE)
應用: 遠程外設(工業(yè)控制,相機,數(shù)據(jù)訪問)
內部開關:
電流限制: 1.1A
電源電壓: 0 V ~ 57 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)裸露焊盤
供應商設備封裝: 20-TSSOP-EP
包裝: 管件
NCP1081
http://onsemi.com
15
 DCDC Converter Controller
The NCP1081 implements a current mode DCDC converter controller which is illustrated in Figure 13.
VDDL
FB
CS
360 mV
Oscillator
COMP
SS
Gate
Driver
PWM comp
OSC
VDDL
VDDL
Blanking
time
Current Slope
Compensation
2
Softstart
R
S
Q
1.45 V
1.2 V
Current limit
comp
 0
9 V LDO
3.3 V LDO
GATE
VDDH
ARTN
VPORTP
Set
CLK
Reset
CLK
Figure 13. DCDC Controller Block Diagram
5 kW
10 mA
11 kW
5 mA
 Internal VDDH and VDDL Regulators and Gate Driver
An internal linear regulator steps down the VPORTP
voltage to a 9 V output on the VDDH pin. VDDH supplies
the internal gate driver circuit which drives the GATE pin
and the gate of the external power MOSFET. The NCP1081
gate driver supports an external MOSFET with high Vth and
high input gate capacitance. A second LDO regulator steps
down the VDDH voltage to a 3.3 V output on VDDL. VDDL
powers the analog circuitry of the DC-DC controller and
nCLASS_AT blocks. Moreover it can provide current to
light a LED connected on the nCLASS_AT pin.
In order to prevent uncontrolled operations, both regulators
include poweronreset (POR) detectors which prevent the
DCDC controller from operating when either VDDH or
VDDL is too low. In addition, an overvoltage lockout
(OVLO) on the VDDH supply disables the gate driver in case
of an openloop converter with a configuration using the bias
winding of the transformer (see Figure 4).
Both VDDH and VDDL regulators turn on as soon as
VPORT reaches the Vuvlo_on threshold.
 Error Amplifier
In nonisolated converter topologies, the high gain
internal error amplifier of the NCP1081 and the internal
1.2 V reference voltage regulate the DCDC output voltage.
In this configuration, the feedback loop compensation
network should be inserted between the FB and COMP pins
as shown in Figures 3, 4 and 5.
In isolated topologies the error amplifier is not used
because it is already implemented externally with the shunt
regulator on the secondary side of the DCDC controller
(see Figure 2). Therefore the FB pin must be strapped to
ARTN and the output transistor of the optocoupler has to
be connected on the COMP pin where an internal 5 kW
pullup resistor is tied to the VDDL supply (see Figure 13).
 SoftStart
The softstart function provided by the NCP1081 allows
the output voltage to ramp up in a controlled fashion,
eliminating output voltage overshoot. This function is
programmed by connecting a capacitor C
SS
 between the SS
and ARTN pins.
While the DCDC controller is in POR, the capacitor C
SS
is fully discharged. After coming out of POR, an internal
current source of 5 mA typically starts charging the capacitor
C
SS
 to initiate softstart. When the voltage on SS pin has
reached 0.45 V (typical), the gate driver is enabled and
DCDC operation starts with a duty cycle limit which
increases with the SS pin voltage. The softstart function is
finished when the SS pin voltage goes above 1.6 V for which
the duty cycle limit reaches its maximum value of 80
percent.
Softstart can be programmed by using the following
equation:
t
SS
(ms) + 0.23 C
SS
(nF)
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