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參數(shù)資料
| 型號： | NCP4896EVB |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR NCP4896 |
| 設(shè)計資源： | NPC4896 Demo Brd BOM NCP4896 Demo Brd Schematic |
| 標準包裝： | 1 |
| 放大器類型： | AB 類 |
| 輸出類型： | 1-通道（單聲道）帶單聲道耳機 |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 1.08W x 1 @ 8 歐姆; 176mW x 1 @ 16 歐姆 |
| 電源電壓： | 2.2 V ~ 5.5 V |
| 板類型： | 完全填充 |
| 已用 IC / 零件： | NCP4896 |
| 已供物品： | 板 |
| 其它名稱： | NCP4896EVBOS |
NCP4896
http://onsemi.com
11
APPLICATION INFORMATION
Detailed Description
The NCP4896 audio amplifier can operate from 2.2 V
until 5.5 V power supply. It delivers 320 mW rms output
power to 4.0
W load (VP = 2.6 V) and 1.0 W rms output
power to 8.0
W load (VP = 5.0 V).
The structure of the NCP4896 is basically composed of
two identical internal power amplifiers. Both are externally
configurable with gainsetting resistors Rin and RF (the
closedloop gain is fixed by the ratios of these resistors).
So the load is driven differentially through OUTA and
OUTB outputs. This configuration eliminates the need for
an output coupling capacitor.
Internal Power Amplifier
The output Pmos and Nmos transistors of the amplifier
were designed to deliver the output power of the
specifications without clipping. The channel resistance
(Ron) of the Nmos and Pmos transistors does not exceed
0.6
W when they drive current.
The structure of the internal power amplifier is
composed of three symmetrical gain stages, first and
medium gain stages are transconductance gain stages to
obtain maximum bandwidth and DC gain.
TurnOn and TurnOff Transitions
A cycle with a turnon and turnoff transition is
illustrated with plots that show both single ended signals on
the previous page.
In order to eliminate “pop and click” noises during
transitions, output power in the load must be slowly
established or cut. When logic high is applied to the
shutdown
pin, the bypass voltage begins to rise
exponentially and once the output DC level is around the
common mode voltage, the gain is established slowly
(20 ms). This way to turnon the device is optimized in
terms of rejection of “pop and click” noises.
A theoretical value of turnon time at 25
°C is given by
the following formula.
Cby: bypass capacitor
R: internal 150 k resistor with a 25% accuracy
Ton = 0.95 * R * Cby
The device has the same behavior when it is turnedoff
by a logic low on the shutdown pin. During the shutdown
mode, amplifier outputs are connected to the ground.
However, to cut totally the output audio signal, you only
need to wait for 20 ms.
Shutdown Function
The device enters shutdown mode when the shutdown
signal is low. During the shutdown mode, the Dc quiescent
current of the circuit is typically 10 nA.
Current Limit Circuit
The
maximum
output
power
of
the
circuit
(Porms = 1.0 W, VP = 5.0 V, RL = 8.0
W) requires a peak
current in the load of 500 mA.
In order to limit the excessive power dissipation in the
load when a shortcircuit occurs, the current limit in the
load is fixed to 800 mA. The current in the four output MOS
transistors are realtime controlled, and when one current
exceeds 800 mA, the gate voltage of the MOS transistor is
clipped and no more current can be delivered.
SingleEnded Operation
In SE mode, the load is driven from the primary amplifier
output (OUTA). The gain is set by the ration between RF
and Ri.
SE Gain
+ Rf
Ri
In this SE mode, an output capacitor (Co) is required to
block the common mode voltage at the output of the
amplifier, thus avoiding DC currents in the load. As for the
high pass filter due to the input capacitor and the Ri resistor,
the load gives with Co another first order high pass filter,
the cutoff frequency of which is given by:
Fc
+
1
2
pRL @ Co
SE/BTL Operation
Due to the internal control of each amplifier through
SE/BTL pin, the NCP4896 allows a cost saving for
application which requires to drive a example an 8.0
W
BTL and a
32 W SingleEnded load.
The internal circuitry avoids “pop and click” noises that
could occur in both BTL and SingledEnded loads during
transitions from SE to BTL and BTL to SE.
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