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參數(shù)資料
| 型號： | NCP5220MNR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3−in−1 PWM Dual Buck and Linear Power Controller |
| 中文描述： | 2 A SWITCHING CONTROLLER, 566 kHz SWITCHING FREQ-MAX, DSO20 |
| 封裝： | 6 X 5 MM, LEAD FREE, DFN-20 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 182K |
| 代理商： | NCP5220MNR2G |
NCP5220
http://onsemi.com
14
APPLICATION INFORMATION
Application Circuit
Figure 20, on the following page, shows the typical
application circuit for NCP5220. The NCP5220 is
specifically designed as a total power solution for the MCH
and DDR memory system. This diagram contains NCP5220
for driving four external NCh FETs to form the DDR
memory supply voltage (VDDQ) and the MCH regulator.
Output Inductor Selection
The value of the output inductor is chosen by balancing
ripple current with transient response capability. A value of
1.7 H will yield about 3.0 A peakpeak ripple current when
converting from 5.0 V to 2.5 V at 250 kHz. It is important
that the rated inductor current is not exceeded during full
load, and that the saturation current is not less than the
expected peak current. Low ESR inductors may be required
to minimize DC losses and temperature rise.
Input Capacitor Selection
Input capacitors for PWM power supplies are required to
provide a stable, low impedance source node for the buck
regulator to convert from. The usual practice is to use a
combination of electrolytic capacitors and multilayer
ceramic capacitors to provide bulk capacitance and high
frequency noise suppression. It is important that the
capacitors are rated to handle the AC ripple current at the
input of the buck regulators, as well as the input voltage. In
the NCP5220 the DDQ and MCH regulators are interleaved
(out of phase by 180 degrees) to reduce the peak AC input
current.
Output Capacitor Selection
Output capacitors are chosen by balancing the cost with
the requirements for low output ripple voltage and transient
voltage. Low ESR electrolytic capacitors can be effective at
reducing ripple voltage at 250 kHz. Low ESR ceramic
capacitors are most effective at reducing output voltage
excursions caused by fast load steps of system memory and
the memory controller.
Power MOSFET Selection
Power MOSFETs are chosen by balancing the cost with
the requirements for the current load of the memory system
and the efficiency of the converter provided. The selections
criteria can be based on drainsource voltage, drain current,
onresistance R
DS(on)
and input gate capacitance. Low
R
DS(on)
and high drain current power MOSFETs are usually
preferred to achieve the high current requirement of the
DDR memory system and MCH, as well as the high
efficiency of the converter. The tradeoff is a corresponding
increase in the input gate capacitor of the power MOSFETs.
PCB Layout Considerations
With careful PCB layout the NCP5220 can supply 20 A or
more of current. It is very important to use wide traces or
large copper shapes to carry current from the input node
through the MOSFET switches, inductor and to the output
filters and load. Reducing the length of high current nodes
will reduce losses and reduce parasitic inductance. It is
usually best to locate the input capacitors the MOSFET
switches and the output inductor in close proximity to
reduce DC losses, parasitic inductance losses and radiated
EMI.
The sensitive voltage feedback and compensation
networks should be placed near the NCP5220 and away
from the switch nodes and other noisy circuit elements.
Placing compensation components near each other will
minimize the loop area and further reduce noise
susceptibility.
Optional Boost Voltage Configuration
The charge pump circuit in Figure 19 can be used instead
of boost voltage scheme of Figure 20. The advantage in
Figure 19 is the elimination of the requirement for the Zener
clamp.
SW_DDQ
BG_DDQ
TG_DDQ
BOOT
5VDUAL
COMP_1P5
TG_1P5
BG_1P5
GND_1P5
SLP_S3
NCP5220
20
19
18
17
16
15
14
13
12
11
5VDUAL
TP2
R2
4.7
R3
1 k
R4
4.7
3
4
1
3
4
1
DPAK
Q2
NTD40N03
Q2
NTD40N03
D1
BAT54HT1
L
D2
BAT54HT1
C4
100 nF
12VATX
TP2
2.5 VDDQ
TP5
C6
4.7
F
C7
2200
F
+
+2200
F
VDDQ
R15
1 k
Figure 19. Charge Pump Circuit at BOOT Pin
D2
BAT54HT1
5VDUAL
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| NCP5222 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:High Performance Dual-Channel / Two-Phase Synchronous Buck Controller for Notebook Power System |
| NCP5222GEVB | 功能描述:電源管理IC開發(fā)工具 NCP5222 EVAL BOARD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| NCP5222MNR2G | 功能描述:DC/DC 開關(guān)控制器 DUAL SYN BUCK CONTROLLER RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5228 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Synchronous Buck Controller with Auto Power Saving |
| NCP5228MNTWG | 制造商:ON Semiconductor 功能描述:Notebook DDR Controller |
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