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NCP5306
http://onsemi.com
15
PWRGD
low
ééé
ééé
V
LOWER
ééé
ééé
1.975 V
V
OUT
HIGH
LOW
PWRGD
5%
+5%
5%
+5%
Figure 19. PWRGD Assertion Window
PWRGD
low
PWRGD
high
Figure 20. Adjusting the PWRGD Threshold
V
OUT
R1
R2
PWRGDS
Since the internally
set thresholds for PWRGDS are
VID/2 for the lower threshold and a fixed 1.975V for the
upper threshold, a simple equation can be provided to assist
the designer in selecting a resistor divider to provide the
desired PWRGD performance.
VLOWER
VVID
2
1.975 V
R1
R2
R1
VUPPER
The logic circuitry inside the chip sets PWRGD low only
after a delay period has been passed. A “power bad” event
does not cause PWRGD to go low unless it is sustained
through the delay time of 500
μ
s. If the anomaly disappears
before the end of the delay, the PWRGD output will never
be set low.
In order to use the PWRGD pin as specified, the user is
advised to connect external resistors as necessary to limit the
current into this pin to 4 mA or less.
Undervoltage Lockout
The NCP5306 includes an undervoltage lockout circuit.
This circuit keeps the IC’s output drivers low until V
CC
applied to the IC reaches 9 V. The GATE outputs are disabled
when V
CC
drops below 8 V.
Soft Start and Hiccup Mode
At initial power
up, both SS and COMP voltages are zero.
The total SS capacitance will begin to charge with a current
of 160
μ
A. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper start
up behavior. All GATE outputs are
held low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally. In current limit, the internal fault latch will
initiate a 5
μ
A discharge current on the SS pin, and the
internal clamp will discharge the capacitor connected to the
COMP pin at a similar rate. This performance will result in
GATE pulses being generated until the overcurrent
condition reoccurs and the discharge/soft start cycle begins
anew.
Current Limit
Two levels of over
current protection are provided. First,
if the voltage on the Current Sense pins (CSx) exceeds
CS
REF
by more than a fixed threshold (Single Pulse Current
Limit), the PWM comparator is turned off. This provides
fast peak current protection for individual phases. Second,
the individual phase currents are summed and low
pass
filtered to compare an averaged current signal to a user
adjustable voltage on the OCSET pin. If the OCSET voltage
is exceeded, the fault latch trips and the Soft Start capacitor
discharges until the Soft Start pin reaches 0.3 V. Then Soft
Start begins. The converter will continue to operate in a low
average current hiccup
mode until the fault condition is
corrected.
Fault Protection Logic
The NCP5306 includes fault protection circuitry to
prevent harmful modes of operation from occurring. The
fault logic is described in Table 1.
Gate Outputs
The NCP5306 is designed to operate with external gate
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5 ns.
Digital to Analog Converter (DAC)
The output voltage of the NCP5306 is set by means of a
5
bit, 1% DAC. The DAC pins are internally pulled up to a
3.3 V rail through a blocking diode and a set of 50 k
Ω
resistors. The blocking diode allows external pull up to a
bias voltage greater than 3.3 V and less than 13 V.
The output of the DAC is described in the Electrical
Characteristics section of the data sheet. These outputs are
consistent with the latest VRM and processor specifications.
The DAC output is equal to the VID code specification.
In order to produce a workable power supply using the
NCP5306, the designer is expected to use AVP as described
earlier to position the output voltage below the DAC output,
resulting in an output voltage somewhere in the middle of
the acceptable range.