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參數(shù)資料
| 型號： | NCT210RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 184K |
| 描述： | IC TEMP SENSOR LOC/REM 16QSOP |
| 標準包裝： | 2,500 |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內部和外部 |
| 感應溫度： | -65°C ~ 127°C |
| 精確度： | ±3°C 本地（最大），±5°C 遠程（最大） |
| 拓撲： | ADC（三角積分型），比較器，寄存器庫 |
| 輸出類型： | 2 線 SMBus? |
| 輸出警報： | 是 |
| 輸出風扇： | 無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
NCT210
http://onsemi.com
10
Table 9. CONVERSION RATE REGISTER CODE
Data
Conversion/
Sec
Average Supply Current
mA Typ at V
CC
= 3.3 V
0x00
0.0625
150
0x01
0.125
150
0x02
0.25
150
0x03
0.5
150
0x04
1
150
0x05
2
150
0x06
4
160
0x07
8
180
0x08 to 0xFF
Reserved
Limit Registers
The NCT210 has four limit registers to store local and
remote and high and low temperature limits. These registers
can be written to and read back over the SMBus. The high
limit registers perform a > comparison, while the low limit
registers perform a < comparison. For example, if the high
limit register is programmed as a limit of 80癈, measuring
81癈 results in an alarm condition.
One-shot Register
The one-shot register is used to initiate a single conversion
and comparison cycle when the NCT210 is in standby mode,
after which the device returns to standby. This is not a data
register as such, and it is the write operation that causes the
one-shot conversion. The data written to this address is
irrelevant and is not stored.
Serial Bus Interface
Control of the NCT210 is carried out via the serial bus.
The NCT210 is connected to this bus as a slave device, under
the control of a master device. Note that the SMBus and SCL
pins are three-stated when the NCT210 is powered down and
will not pull down the SMBus.
Address Pins
In general, every SMBus device has a 7-bit device address
(except for some devices that have extended 10-bit
addresses). When the master device sends a device address
over the bus, the slave device with that address responds.
The NCT210 has two address pins, ADD0 and ADD1, to
allow selection of the device address so that several
NCT210s can be used on the same bus, and/or to avoid
conflict with other devices. Although only two address pins
are provided, these are three-state and can be grounded, left
unconnected, or tied to V
DD
so that a total of nine different
addresses are possible, as shown in Table 10.
It should be noted that the state of the address pins is only
sampled at powerup, so changing them after powerup has no
effect.
Table 10. DEVICE ADDRESSES (Note 1)
ADD0
ADD1
Device Address
0
0
0011 000
0
NC
0011 001
0
1
0011 010
NC
0
0101 001
NC
NC
0101 010
NC
1
0101 011
1
0
1001 100
1
NC
1001 101
1
1
1001 110
1. ADD0 and ADD1 are sampled at powerup only.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high-to-low transition
on the serial data line SDATA, while the serial
clock line SCLK remains high. This indicates that
an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus
an R/W
bit, which determines the direction of the
data transfer, that is, whether data will be written
to or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge Bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W
bit is a 0, the master writes
to the slave device. If the R/W
bit is a 1, the
master reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, because a low-to-high
transition when the clock is high can be interpreted
as a stop signal. The number of data bytes that can
be transmitted over the serial bus in a single read
or write operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
then takes the data line low during the low period
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