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參數(shù)資料
| 型號： | NCV2902DTBR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP QUAD DIFF INPUT 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 0.6 V/µs |
| 增益帶寬積： | 1MHz |
| 電流 - 輸入偏壓： | 90nA |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 1.4mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 32 V，±1.5 V ~ 16 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | NCV2902DTBR2GOSDKR |
LM324, LM324A, LM224, LM2902, LM2902V, NCV2902
http://onsemi.com
6
CIRCUIT DESCRIPTION
The LM324 series is made using four internally
compensated, twostage operational amplifiers. The first
stage of each consists of differential input devices Q20 and
Q18 with input buffer transistors Q21 and Q17 and the
differential to single ended converter Q3 and Q4. The first
stage performs not only the first stage gain function but also
performs the level shifting and transconductance reduction
functions. By reducing the transconductance, a smaller
compensation capacitor (only 5.0 pF) can be employed, thus
saving chip area. The transconductance reduction is
accomplished by splitting the collectors of Q20 and Q18.
Another feature of this input stage is that the input common
mode range can include the negative supply or ground, in
single supply operation, without saturating either the input
devices or the differential to singleended converter. The
second stage consists of a standard current source load
amplifier stage.
Figure 2. Large Signal Voltage Follower Response
VCC = 15 Vdc
RL = 2.0 kW
TA = 25°C
5.0
ms/DIV
1.0
V/DIV
Each amplifier is biased from an internalvoltage
regulator which has a low temperature coefficient thus
giving each amplifier good temperature characteristics as
well as excellent power supply rejection.
Single Supply
Split Supplies
VCC
VEE/GND
3.0 V to VCC(max)
1
2
3
4
VCC
1
2
3
4
VEE
1.5 V to VCC(max)
1.5 V to VEE(max)
Figure 3.
70
60
50
40
30
20
10
0
1.0
10
100
10000
LOAD CAPACITANCE (pF)
Phase Margin
Figure 4. Gain and Phase Margin
1000
70
60
50
40
30
20
10
0
GAIN
MARGIN
(dB)
PHASE
MARGIN
(
°)
Gain Margin
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