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參數(shù)資料
| 型號(hào)： | NET+50-BIT |
| 廠商： | Digi International |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7 MPU 32BIT 208BGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | NET+ARM® |
| 應(yīng)用： | 網(wǎng)絡(luò)處理器 |
| 核心處理器： | ARM7 |
| 程序存儲(chǔ)器類型： | 外部程序存儲(chǔ)器 |
| 控制器系列： | NET+50 |
| RAM 容量： | 16K x 8 |
| 接口： | EBI/EMI，以太網(wǎng)，DMA，HDLC，IEEE1284/ENI，SPI，UART |
| 輸入/輸出數(shù)： | 40 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-LFBGA |
| 包裝： | 托盤 |
| 供應(yīng)商設(shè)備封裝： | 208-BGA（15x15） |
Hardware Specifications
40 programmable I/O pins
16 general purpose input only pins
36 programmable edge or level
interrupts
G E N E R A L
P U R P O S E
I / O
10/100 Mbs MII PHY
Full- or half-duplex
Station, broadcast, multicast
address detection and filtering
128B transmit buffer
2 kB receive buffer
Intelligent receive side-buffer size
selection
External CAM filtering support
I N T E G R A L
1 0 / 1 0 0
E T H E R N E T
M A C
44 MHz bus speed
5 independent programmable
chip selects
Supports 8-, 16-, 32-bit peripherals
Supports external address decoding
and cycle termination
Supports dynamic bus sizing
(8-, 16-, & 32-bit)
ASYNC and SYNC peripheral timing
All chip selects support SRAM, EDO
DRAM, SDRAM, Flash, EEPROM
without external glue logic
Internal DRAM address multiplexing
Internal refresh controller
256 MB addressing per chip select
Burst-mode support
0-15 wait states per chip select
Bootstrap support
E X TE R N A L B U S I N T E RF A C E /
M E M O RY C O N TR O L L E R
Operating voltage:
- Core: 2.5V ± 10%
- I/O Ring: 3.3V ± 10%
Operating temperature range:
-40 C to 85 C
O T H E R
44 MHz 32-bit ARM CPU
15 general purpose 32-bit registers
32-bit program counter and
status register
5 supervisor modes, 1 user mode
3 2 - B I T
A R M 7 T D M I
R I S C
P R O C E S S O R
8 kB internal cache or 16 kB RAM
4-way set associative
Lockable entries
Write through
O N - C H I P
C A C H E
4 IEEE 1284 parallel ports, host mode
64 K shared RAM ENI interface
(8- or 16-bit)
Full-duplex FIFO mode interface
(8- or 16-bit)
32 B transmit and 32 B receive FIFOs
IEEE 1284/ENI/GPIO INTERFACE
USING SHARED PINS
2 dedicated to Ethernet
transmit/receive
4 dedicated to serial
transmit/receive
2 dedicated to 1284 interface
2 dedicated to external
peripherals
Flexible buffer management
1 0 - C H A N N E L
D M A
C O N T R O L L E R
2 fully independent HDLC/UART/SPI
serial ports
32B transmit and 32B receive FIFOs
Internal programmable bit rate
generators
Bit rates from 75 bps to 230 Kbps
16X mode
Bit rates from 1200 bps to 4 Mbps:
1X mode
Odd, even, or no parity
5, 6, 7 or 8 bits
1 or 2 stop bits
Both internal & external clock
support
Receive side character and buffer
gap timers
4 receive side data match detectors
S E R I A L
P O R T S
2 independent 27-bit programmable
timers
Programmable watch-dog timer
Programmable bus timer
T I M E R S
Simple external crystal
On-board Phase Locked Loop
Supports direct external clock input
C L O C K
G E N E R A T O R
208-pin BGA, 0.8 mm pitch
PQFP
Lead-free; RoHS compliant
P A C K A G E
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