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參數(shù)資料
| 型號(hào)： | NJG1515AVB2-C2 |
| 廠商： | New Japan Radio Co., Ltd. |
| 英文描述： | MS/STANDARD CYLINDRICAL MIL-C-5015 TYPE CONNECTORS, STRAIGHT BODY STYLE, SOLDER TERMINATION, 18 SHELL SIZE, 18-1 INSERT ARRANGEMENT, PLUG GENDER, 10 CONTACTS |
| 中文描述： | 時(shí)分多址天線開關(guān)砷化鎵微波單片集成電路 |
| 文件頁(yè)數(shù)： | 16/18頁(yè) |
| 文件大?。?/td> | 549K |
| 代理商： | NJG1515AVB2-C2 |
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NJG1515AVB2
- 7 -
nTERMINAL INFORMATION
PIN NO.
SYMBOL
DESCRIPTIONS
1
CTL2
High-impedance C-MOS input terminal. This terminal is set to High-Level by
2V~VDD, and Low-Level by +0.6V~0V. In case of open or unstable level,
connect this terminal by 100K
resistor with GND terminal or V
DD terminal.
2
CTL3
High-impedance C-MOS input terminal. This terminal is set to High-Level by
2V~VDD, and Low-Level by +0.6V~0V. In case of open or unstable level,
connect this terminal by 100K
resistor with GND terminal or V
DD terminal.
3
VSS
Negative voltage supply terminal. The negative voltage (-3.5~-2.0V) have to
be supplied on transmitting. Otherwise negative voltage of -2.5~0V can be
used or this terminal can be stayed open, because internal level of this
terminal is automatically set to GND level on receiving. The bypass capacitor
have to be connected with GND terminal for excellent RF performance.
4
EXT2
RF receiving port. An external capacitor of 56pF~100pF is required to block
DC voltage (VDD).
6
EXT1
RF transmitting/receiving port. An external capacitor of 56pF~100pF is
required to block DC voltage (VDD).
8
TX
RF transmitting port. An external capacitor of 56pF~100pF is required to
block DC voltage (VDD).
10
TER2
ANT1 termination port. The influence of ANT1 port to ANT2 port is
suppressed by terminating this port by an appropriate termination. An
external capacitor (5pF) is required to block DC voltage (VDD).
11
ANT1
RF transmitting/receiving port. An external capacitor of 56pF~100pF is
required to block DC voltage (VDD).
13
RX
RF receiving port. An external capacitor of 56pF~100pF is required to block
DC voltage (VDD).
15
ANT2
RF receiving port. An external capacitor of 56pF~100pF is required to block
DC voltage (VDD).
17
TER1
ANT2 termination port. The influence of ANT2 port to ANT1 port is
suppressed by terminating this port with appropriate termination. An external
capacitor (5pF) is required to block DC voltage (VDD).
19
VDD
Positive voltage supply terminal. The positive voltage (2.7~5.0V) have to be
supplied. The bypass capacitor have to be connected with GND terminal for
excellent RF performance.
20
CTL1
High-impedance C-MOS input terminal. This terminal is set to High-Level by
2V~VDD, and Low-Level by +0.6~0V. In case of open or unstable level,
connect this terminal by 100k
resistor with GND terminal or V
DD terminal.
5,7,9,12,
14,16,18
GND
Ground terminal. Please connect this terminal with ground plane as close as
possible for excellent RF performance.
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