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參數(shù)資料
| 型號： | NL17SH126P5T5G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 0K |
| 描述： | IC GATE NONINV BUFFER SOT953 |
| 標(biāo)準(zhǔn)包裝： | 8,000 |
| 邏輯類型： | 緩沖器/線路驅(qū)動器，非反相 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 1 |
| 輸出電流高，低： | 8mA，8mA |
| 電源電壓： | 2 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-953 |
| 供應(yīng)商設(shè)備封裝： | SOT-953 |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2011
August, 2011 Rev. 1
1
Publication Order Number:
NL17SH126/D
NL17SH126
Noninverting 3-State Buffer
The NL17SH126 is an advanced high speed CMOS noninverting
3state buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffered
3state output which provides high noise immunity and stable output.
The NL17SH126 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
NL17SH126 to be used to interface 5 V circuits to 3 V circuits.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
These are PbFree Devices
Figure 1. Pinout (Top View)
VCC
OE
IN A
OUT Y
GND
IN A
OUT Y
EN
OE
Figure 2. Logic Symbol
1
2
3
5
4
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
FUNCTION TABLE
L
H
X
A Input
Y Output
L
H
Z
OE Input
H
L
PIN ASSIGNMENT
1
2
3OE
IN A
GND
4
5VCC
OUT Y
http://onsemi.com
MARKING
DIAGRAM
SOT953
CASE 527AE
J
= Specific Device Code
M
= Month Code
JM
1
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