參數(shù)資料
型號: NL17SHT04P5T5G
廠商: ON Semiconductor
文件頁數(shù): 1/5頁
文件大?。?/td> 0K
描述: IC GATE INV BUFFER SGL SOT953
標(biāo)準(zhǔn)包裝: 8,000
邏輯類型: 逆變器,緩沖器
電路數(shù): 1
輸入數(shù): 1
電源電壓: 3 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: 8mA,8mA
邏輯電平 - 低: 0.53 V ~ 0.8 V
邏輯電平 - 高: 1.4 V ~ 2 V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 7.7ns @ 4.5V ~ 5.5V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應(yīng)商設(shè)備封裝: SOT-953
封裝/外殼: SOT-953
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2011
August, 2011 Rev. 0
1
Publication Order Number:
NL17SHT04/D
NL17SHT04
Inverting Buffer /
CMOS Logic Level Shifter
LSTTLCompatible Inputs
The NL17SHT04 is a single gate inverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logiclevel translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the highvoltage power supply.
The NL17SHT04 input structure provides protection when voltages
up to 7.0 V are applied, regardless of the supply voltage. This allows
the NL17SHT04 to be used to interface 5 V circuits to 3 V circuits.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
High Speed: tPD = 3.8 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @ Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
These are PbFree Devices
IN A
OUT Y
1
VCC
NC
IN A
OUT Y
GND
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
1
2
34
5
http://onsemi.com
MARKING
DIAGRAM
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
PIN ASSIGNMENT
1
2
3NC
IN A
GND
4
5VCC
OUT Y
FUNCTION TABLE
L
H
A Input
Y Output
H
L
SOT953
CASE 527AE
L
= Specific Device Code
M
= Month Code
LM
1
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