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| 型號： | NL17SZ74USG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP D-TYPE LOG US8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 17SZ |
| 功能： | 設(shè)置（預(yù)設(shè)）和復(fù)位 |
| 類型： | D 型 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 1 |
| 頻率 - 時鐘： | 250MHz |
| 延遲時間 - 傳輸： | 2.2ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 32mA，32mA |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFSOP（0.091"，2.30mm 寬） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1126 (CN2011-ZH PDF) |
| 其它名稱： | NL17SZ74USGOSDKR |
NL17SZ74
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol
Parameter
VCC (V)
Test Conditions
TA = 25°C
TA = 55 to 125°C
Units
Min
Typ
Max
Min
Max
fMAX
Maximum Clock
Frequency
(50% Duty Cycle)
(Waveform 1)
1.8 ± 0.15
CL = 15 pF
RD = 1 MW
S1 = Open
75
75
MHz
2.5 ± 0.2
150
150
3.3 ± 0.3
200
200
5.0 ± 0.5
250
250
3.3 ± 0.3
CL = 50 pF,
RD = 500 W, S1 = Open
175
175
5.0 ± 0.5
200
200
tPLH,
tPHL
Propagation Delay,
CP to Q or Q
(Waveform 1)
1.8 ± 0.15
CL = 15 pF
RD = 1 MW
S1 = Open
2.5
6.5
12.5
2.5
13
ns
2.5 ± 0.2
1.5
3.8
7.5
1.5
8.0
3.3 ± 0.3
1.0
2.8
6.5
1.0
7.0
5.0 ± 0.5
0.8
2.2
4.5
0.8
5.0
3.3 ± 0.3
CL = 50 pF,
RD = 500 W, S1 = Open
1.0
3.4
7.0
1.0
7.5
5.0 ± 0.5
1.0
2.6
5.0
1.0
5.5
tPLH,
tPHL
Propagation Delay,
PR or CLR to Q or Q
(Waveform 2)
1.8 ± 0.15
CL = 15 pF
RD = 1 MW
S1 = Open
2.5
6.5
14
2.5
14.5
ns
2.5 ± 0.2
1.5
3.8
9.0
1.5
9.5
3.3 ± 0.3
1.0
2.8
6.5
1.0
7.0
5.0 ± 0.5
0.8
2.2
5.0
0.8
5.5
3.3 ± 0.3
CL = 50 pF,
RD = 500 W, S1 = Open
1.0
3.4
7.0
1.0
7.5
5.0 ± 0.5
1.0
2.6
5.0
1.0
5.5
tS
Setup Time, D to CP
(Waveform 1)
1.8 ± 0.15
CL = 15 pF
RD = 1 MW
S1 = Open
6.5
6.5
ns
2.5 ± 0.2
3.5
3.5
3.3 ± 0.3
2.0
2.0
5.0 ± 0.5
1.5
1.5
3.3 ± 0.3
CL = 50 pF,
RD = 500 W, S1 = Open
2.0
2.0
5.0 ± 0.5
1.5
1.5
tH
Hold Time, D to CP
(Waveform 1)
1.8 ± 0.15
CL = 15 pF
RD = 1 MW
S1 = Open
0.5
0.5
ns
2.5 ± 0.2
0.5
0.5
3.3 ± 0.3
0.5
0.5
5.0 ± 0.5
0.5
0.5
3.3 ± 0.3
CL = 50 pF,
RD = 500 W, S1 = Open
0.5
0.5
5.0 ± 0.5
0.5
0.5
tW
Pulse Width,
CP, CLR, PR
(Waveform 3)
1.8 ± 0.15
CL = 15 pF
RD = 1 MW
S1 = Open
6.0
6.0
ns
2.5 ± 0.2
4.0
4.0
3.3 ± 0.3
3.0
3.0
5.0 ± 0.5
2.0
2.0
3.3 ± 0.3
CL = 50 pF,
RD = 500 W, S1 = Open
3.0
3.0
5.0 ± 0.5
2.0
2.0
tREC
Recover Time
PR; CLR to CP
(Waveform 3)
1.8 ± 0.15
CL = 15 pF
RD = 1 MW
S1 = Open
8.0
8.0
MHz
2.5 ± 0.2
4.5
4.5
3.3 ± 0.3
3.0
3.0
5.0 ± 0.5
3.0
3.0
3.3 ± 0.3
CL = 50 pF,
RD = 500 W, S1 = Open
3.0
3.0
5.0 ± 0.5
3.0
3.0
8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per flipflop). CPD is used to determine the
noload dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
CAPACITANCE (Note 9)
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCC = 5.5 V
7.0
pF
COUT
Output Capacitance
VCC = 5.5 V
7.0
pF
CPD
Power Dissipation Capacitance (Note 10)
Frequency = 10 MHz
VCC = 3.3 V
VCC = 5.0 V
16
21
pF
9. TA = +25°C, f = 1 MHz
10.CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at
no output loading and operating at 50% duty cycle. (See Figure 1) CPD is related to ICCD dynamic operating current by the expression:
ICCD = CPD VCC fin + ICC(static).
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| NL17SZ86/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single 2-Input Exclusive-OR Gate |
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