參數(shù)資料
型號: OM13032,598
廠商: NXP Semiconductors
文件頁數(shù): 74/74頁
文件大?。?/td> 0K
描述: BOARD EVAL LPC11U24
標準包裝: 1
類型: MCU
適用于相關(guān)產(chǎn)品: LPC11U24
所含物品:
其它名稱: 568-8599
LPC11U2X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
9 of 74
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO
port number. The default function after reset is listed first. All port pins have internal
pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 3.
Pin description
Symbol
Pin
HVQFN33
Pin
TFBGA48
Pin
LQ
FP48
Pin
LQ
FP64
Reset
state
Type
Description
RESET/PIO0_0
2
C1
3
4
I; PU
I
RESET — External reset input with 20 ns glitch filter.
A LOW-going pulse as short as 50 ns on this pin
resets the device, causing I/O ports and peripherals to
take on their default states, and processor execution
to begin at address 0. This pin also serves as the
debug select input. LOW level selects the JTAG
boundary scan. HIGH level selects the ARM SWD
debug mode.
In deep power-down mode, this pin must be pulled
HIGH externally. The RESET pin can be left
unconnected or be used as a GPIO pin if an external
RESET function is not needed and Deep power-down
mode is not used.
-
I/O
PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
3C2
4
5
I; PU
I/O
PIO0_1 — General purpose digital input/output pin. A
LOW level on this pin during reset starts the ISP
command handler or the USB device enumeration.
-O
CLKOUT — Clockout pin.
-O
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
-O
USB_FTOGGLE — USB 1 ms Start-of-Frame signal.
PIO0_2/SSEL0/
CT16B0_CAP0
8F1
10
13
I; PU
I/O
PIO0_2 — General purpose digital input/output pin.
-
I/O
SSEL0 — Slave select for SSP0.
-I
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3/USB_VBUS
9
H2
14
19
I; PU
I/O
PIO0_3 — General purpose digital input/output pin. A
LOW level on this pin during reset starts the ISP
command handler. A HIGH level during reset starts
the USB device enumeration.
-I
USB_VBUS — Monitors the presence of USB bus
power.
PIO0_4/SCL
10
G3
15
20
I; IA
I/O
PIO0_4 — General purpose digital input/output pin
(open-drain).
-
I/O
SCL — I2C-bus clock input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register.
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OM13033 制造商:NXP Semiconductors 功能描述:EVAL ARM NGX LPC11U24 制造商:NXP Semiconductors 功能描述:LPC11U24, NGX, KEIL, EVAL BOARD 制造商:NXP Semiconductors 功能描述:LPC11U24, NGX, KEIL, EVAL BOARD; Silicon Manufacturer:NXP; Core Architecture:ARM; Core Sub-Architecture:Cortex-M0; Silicon Core Number:LPC11xxx; Silicon Family Name:LPC11Uxx; Features:Evaluation Board for LPC11U24 Microcontroller; ;RoHS Compliant: Yes
OM13033,598 功能描述:開發(fā)板和工具包 - ARM NGX LPC11U24 Eval Board RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V
OM13033598 制造商:NXP Semiconductors 功能描述:EVAL ARM NGX LPC11U24
OM13034,598 制造商:NXP Semiconductors 功能描述:EVAL, IAR, LPC1347, J-LINK LITE 制造商:NXP Semiconductors 功能描述:EVAL, IAR, LPC1347, J-LINK LITE, Silicon Manufacturer:NXP, Core Architecture:ARM 制造商:NXP Semiconductors 功能描述:EVAL, IAR, LPC1347, J-LINK LITE, Silicon Manufacturer:NXP, Core Architecture:ARM, Core Sub-Architecture:Cortex-M3, Silicon Core Number:LPC1347, Silicon Family Name:LPC1300, Kit Contents:Evaluation Board for LPC1347 , RoHS Compliant: Yes
OM13034598 制造商:NXP Semiconductors 功能描述:EVAL IAR LPC1347 J-LINK LITE