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| 型號： | OP177GSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP GP PREC LN 8SOIC |
| 產(chǎn)品變化通告： | OP07, OP177 Redesign Change 19/Jul/2011 |
| 設計資源： | AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039) DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040) DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041) AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048) Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061) |
| 標準包裝： | 1,000 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 0.3 V/µs |
| 增益帶寬積： | 600kHz |
| 電流 - 輸入偏壓： | 1.2nA |
| 電壓 - 輸入偏移： | 20µV |
| 電流 - 電源： | 1.6mA |
| 電壓 - 電源，單路/雙路(±)： | 6 V ~ 36 V，±3 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
Data Sheet
OP177
Rev. G | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP177F
OP177G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
INPUT OFFSET VOLTAGE
VOS
10
25
20
60
μV
LONG-TERM INPUT OFFSET1
Voltage Stability
ΔVOS/time
0.3
0.4
μV/mo
INPUT OFFSET CURRENT
IOS
0.3
1.5
0.3
2.8
nA
INPUT BIAS CURRENT
IB
0.2
+1.2
+2
0.2
+1.2
+2.8
nA
INPUT NOISE VOLTAGE
en
118
150
118
150
nV rms
INPUT NOISE CURRENT
in
3
8
3
8
pA rms
INPUT RESISTANCE
Differential Mode3
RIN
26
45
18.5
45
M
INPUT RESISTANCE COMMON MODE
RINCM
200
G
INPUT VOLTAGE RANGE4
IVR
±13
±14
±13
±14
V
COMMON-MODE REJECTION RATIO
CMRR
VCM = ±13 V
130
140
115
140
dB
POWER SUPPLY REJECTION RATIO
PSRR
VS = ±3 V to ±18 V
115
125
110
120
dB
LARGE SIGNAL VOLTAGE GAIN
AVO
5000
12,000
2000
6000
V/mV
OUTPUT VOLTAGE SWING
VO
RL ≥ 10 k
±13.5
±14.0
±13.5
±14.0
V
RL ≥ 2 k
±12.5
±13.0
±12.5
±13.0
V
RL ≥ 1 k
±12.0
±12.5
±12.0
±12.5
V
SLEW RATE2
SR
RL ≥ 2 k
0.1
0.3
0.1
0.3
V/μs
CLOSED-LOOP BANDWIDTH2
BW
AVCL = 1
0.4
0.6
0.4
0.6
MHz
OPEN-LOOP OUTPUT RESISTANCE
RO
60
POWER CONSUMPTION
PD
VS = ±15 V, no load
50
60
50
60
mW
VS = ±3 V, no load
3.5
4.5
3.5
4.5
mW
SUPPLY CURRENT
ISY
VS = ±15 V, no load
1.6
2
1.6
2
mA
OFFSET ADJUSTMENT RANGE
RP = 20 k
±3
mV
1
Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 μV.
2
Sample tested.
3
Guaranteed by design.
4
Guaranteed by CMRR test condition.
5
To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at 10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
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