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參數(shù)資料
| 型號： | OP221NBC |
| 英文描述： | Voltage-Feedback Operational Amplifier |
| 中文描述： | 電壓反饋運算放大器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 193K |
| 代理商： | OP221NBC |
REV. A
–4–
OP221–SPECIFICATIONS
.
OP221A/E
Typ
OP221G
Typ
Parameter
Symbol
Conditions
Min
Max
Min
Max
Unit
Input Offset
Voltage Match
V
OS
I
B
+
100
400
400
800
μ
V
Average Noninverting
Bias Current
V
CM
= 0
100
140
nA
Input Offset
Voltage Tracking
IC
V
OS
1
2
3
5
μ
V
°
C
Noninverting Input
Offset Current
I
OS
+
V
CM
= 0
3
7
6
12
nA
Common-Mode
Rejection Ratio
Match (Note 1)
Power Supply
Rejection Ratio
Match (Note 1)
CMRR
V
CM
= –15 V to 13.2 V
87
90
72
80
dB
PSRR
26
140
μ
V/V
NOTES
1
CMRR is 20 log
10
V
CM
/
CME, where V
CM
is the voltage applied to both noninverting inputs and
CME is the difference in common-mode input-referred error.
2
PSRR is: Input-Referred Differential Error
V
S
(Matching Characteristics at V
s
= 15 V, –55 C
≤
T
A
≤
+125 C for OP221A,
–25 C
≤
T
A
≤
+85 C for OP221E, –40 C
≤
T
A
≤
+85 C for OP221G, unless otherwise noted.
Grades E and G are sample tested.)
.
OP221N
Limit
Parameter
Symbol
Conditions
Unit
μ
V Max
Input Offset Voltage
V
OS
I
OS
I
B
IVR
200
Input Offset Current
V
CM
= 0
V
CM
= 0
V+ = 5 V, V– = 0 V
V
S
=
±
15 V
V– = 0 V, V+ = 5 V,
0 V
≤
V
CM
≤
3.5 V
V
S
=
±
15 V
–15 V
≤
V
CM
≤
13.5 V
V
S
=
±
2.5 V to
±
15 V
V– = 0 V, V+ = 5 V to 30 V
V
S
=
±
15 V
R
L
= 10 k
V+ = 5 V, V– = 0 V, R
L
= 10 k
V
S
= 15 V, R
L
= 10 k
V
S
=
±
2.5 V, No Load
V
S
=
±
15 V, No Load
3.5
nA Max
Input Bias Current
85
nA Max
Input Voltage Range
0/3.5
–15/13.5
88
V Min/Max
V Min
Common-Mode
Rejection Ratio
CMRR
dB Min
93
12.5
22.5
Power Supply
Rejection Ratio
Large-Signal
Voltage Gain
Output Voltage Swing
PSRR
V/mV Min
Avo
1500
V/mV Max
V
O
0.7/4.1
±
13.8
560
810
V Min/Max
V Min
μ
A Max
Supply Current
(Both Amplifiers)
I
SY
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
Wafer Test Limits at V
s
= 2.5 V to 15 V, T
A
= 25 C, unless otherwise noted.
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