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| 型號(hào)： | OP482 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad Low Power, High Speed JFET Operational Amplifiers(低功耗,高速四運(yùn)算放大器) |
| 中文描述： | 四路低功耗，高速場(chǎng)效應(yīng)運(yùn)算放大器（低功耗，高速四運(yùn)算放大器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 267K |
| 代理商： | OP482 |
–2–
OP282/OP482–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V
S
=
6
15.0 V, T
A
= +25
8
C unless otherwse noted)
Parameter
Symbol
Conditions
Min
T yp
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
V
OS
OP282
OP282, –40
≤
T
A
≤
+85
°
C
OP482
OP482, –40
≤
T
A
≤
+85
°
C
V
CM
= 0 V
V
CM
= 0 V, Note 1
V
CM
= 0 V
V
CM
= 0 V, Note 1
0.2
3
4.5
4
6
100
500
50
250
+15
mV
mV
mV
mV
pA
pA
pA
pA
V
dB
V/mV
V/mV
μ
V/
°
C
pA/
°
C
Offset Voltage
V
OS
0.2
Input Bias Current
I
B
3
Input Offset Current
I
OS
1
Input Voltage Range
Common-Mode Rejection
Large Signal Voltage Gain
–11
70
20
15
CMR
A
VO
–11 V
≤
V
CM
≤
+15 V, –40
≤
T
A
≤
+85
°
C
R
L
= 10 k
R
L
= 10 k
, –40
≤
T
A
≤
+85
°
C
90
Offset Voltage Drift
Bias Current Drift
V
OS
/
T
I
B
/
T
10
8
OUT PUT CHARACT ERIST ICS
Output Voltage Swing
Short Circuit Limit
V
O
I
SC
R
L
= 10 k
Source
Sink
f = 1 MHz
–13.5
3
–8
±
13.9
10
–12
200
13.5
V
mA
mA
Open-Loop Output Impedance
Z
OUT
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
=
±
4.5 V to
±
18 V,
–40
≤
T
A
≤
+85
°
C
V
O
= 0 V, 40
≤
T
A
≤
+85
°
C
25
210
316
250
±
18
μ
V/V
μ
A
V
Supply Current/Amplifier
Supply Voltage Range
I
SY
V
S
±
4.5
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling T ime
Gain Bandwidth Product
Phase Margin
SR
BW
P
t
S
GBP
O
R
L
= 10 k
1% Distortion
T o 0.01%
7
9
125
1.6
4
55
V/
μ
s
kHz
μ
s
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
e
n
p-p
e
n
i
n
0.1 Hz to 10 Hz
f = 1 kHz
1.3
36
0.01
μ
V p-p
nV/
√
Hz
pA/
√
Hz
NOT E
1
T he input bias and offset currents are tested at T
A
= T
J
= +85
°
C. Bias and offset currents are guaranteed but not tested at –40
°
C.
Specifications subject to change without notice.
WAFER TEST LIMTS
(@ V
S
=
6
15.0 V, T
A
= +25
8
C unless otherwse noted)
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
1
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current/Amplifier
V
OS
V
OS
I
B
I
OS
OP282
OP482
V
CM
= 0 V
V
CM
= 0 V
3
4
100
50
–11, +15
70
316
20
±
13.5
250
mV max
mV max
pA max
pA max
V min/max
dB min
μ
V/V
V/mV min
V min
μ
A max
CMRR
PSRR
A
VO
V
O
I
SY
–11 V
≤
V
CM
≤
+15 V
V =
±
4.5 V to
±
18 V
R
L
= 10 k
R
L
= 10 k
V
O
= 0 V, R
L
=
∞
NOT ES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1
Guaranteed by CMR test.
Specifications subject to change without notice.
REV. B
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