參數(shù)資料
型號(hào): OPA2690IDBV
英文描述: Dual, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable
中文描述: 雙路,寬帶,電壓反饋運(yùn)算放大器具有禁用
文件頁(yè)數(shù): 21/30頁(yè)
文件大?。?/td> 494K
代理商: OPA2690IDBV
"#$%
SBOS238D JUNE 2002 REVISED DECEMBER 2004
www.ti.com
21
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including
additional
external
capacitance
recommended to improve ADC linearity. A high-speed,
high open-loop gain amplifier like the OPA2690 can be
very susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the open-loop output resistance
of the amplifier is considered, this capacitive load
introduces an additional pole in the signal path that can
decrease the phase margin. Several external solutions to
this problem have been suggested. When the primary
considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series-isolation resistor
between the amplifier output and the capacitive load. This
does not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the
capacitive load pole, thus increasing the phase margin and
improving stability.
which
may
be
The Typical Characteristics show the recommended R
S
versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads greater
than 2pF can begin to degrade the performance of the
OPA2690. Long PC board traces, unmatched cables, and
connections to multiple devices can easily exceed this
value. Always consider this effect carefully, and add the
recommended series resistor as close as possible to the
OPA2690 output pin (see the
Board Layout Guidelines
section).
The criterion for setting this R
S
resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA2690 operating in a gain of +2, the frequency
response at the output pin is already slightly peaked
without the capacitive load requiring relatively high values
of R
S
to flatten the response at the load. Increasing the
noise gain will reduce the peaking as described previously.
The circuit of Figure 13 demonstrates this technique,
allowing lower values of R
S
to be used for a given
capacitive load.
1/2
OPA2690
402
175
402
+5V
50
50
C
LOAD
R
NG
V
O
R
5V
Powersupply decoupling
not shown.
Figure 13. Capacitive Load Driving with Noise
Gain Tuning
This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain,
increasing the unloaded phase margin for the op amp.
Although this technique will reduce the required R
S
resistor for a given capacitive load, it does increase the
noise at the output. It also will decrease the loop gain,
slightly decreasing the distortion performance. If, however,
the dominant distortion mechanism arises from a high R
S
value, significant dynamic range improvement can be
achieved using this technique. Figure 14 shows the
required R
S
versus C
LOAD
parametric on noise gain using
this technique. This is the circuit of Figure 13 with R
NG
adjusted to increase the noise gain (increasing the phase
margin) then sweeping C
LOAD
and finding the required R
S
to get a flat frequency response. This plot also gives the
required R
S
versus C
LOAD
for the OPA2690 operated at
higher signal gains without R
NG
.
100
90
80
70
60
50
40
30
20
10
0
Capacitive Load (pF)
1
10
100
1000
R
S
(
NG = 2
NG = 3
NG = 4
Figure 14. Required R
S
vs Noise Gain
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