參數(shù)資料
型號: OPA655U
元件分類: 運動控制電子
英文描述: Wideband, Unity Gain Stable, FET-Input OPERATIONAL AMPLIFIER
中文描述: 寬帶,單位增益穩(wěn)定,F(xiàn)ET輸入運算放大器
文件頁數(shù): 10/14頁
文件大?。?/td> 222K
代理商: OPA655U
OPA655
10
response. Figure 5 shows the analysis circuit for setting the
feedback compensation capacitor, C
F
, while Figure 6 shows
the Bode analysis.
to set the high frequency pole for the noise gain at its
intersection with the open loop gain response.
If the 1/2
π
R
F
C
F
pole for the noise gain were set exactly at
the intersection with the amplifier’s open loop gain rolloff,
the circuit would be operating with a 45
°
phase margin
yielding a highly peaked frequency response. To reduce
broadband noise and pulse response ringing, it is preferable
to set this pole at a slightly lower frequency than the
simplified analysis shown above. A second order analysis
for the transimpedance configuration yields the following
results to achieve a maximally flat Butterworth characteris-
tic for the transimpedance frequency response. Using the
OPA655’s gain bandwidth product (GBW) in Hz, define a
variable:
Then, the required C
F
to produce a maximally flat frequency
response is:
and the resulting –3dB bandwidth for the transimpedance
gain will be:
Figure 7 plots the required C
F
vs R
F
(given different values
for the diode capacitance) to achieve the maximally flat
response. Figure 8 plots the resulting bandwidth for the same
range of R
F
and C
D
assuming C
F
has been set as shown in
Figure 7. These plots include a parasitic input capacitance of
2.2pF in parallel with the diode capacitance (C
D
). Very low
effective values for the compensation capacitor (C
F
) can be
produced by splitting the feedback resistor as shown on the
front page application circuit.
The total capacitance to ground on the inverting input of the
OPA655 will set the source capacitance (C
S
) for analysis
purposes. C
S
is the sum of the diode capacitance (C
D
), the
common mode input capacitance C
CM
and the differential
input capacitance (C
DIFF
). Looking at the Bode analysis for
the transimpedance configuration, at low frequencies the
noise gain is 1 (0dB) but will increase for frequencies above
1/2
π
(R
F
(C
S
+ C
F
)) due to the zero formed by the capaci-
tance on the inverting node. It is important to note that the
gain for the op amp input noise voltage will increase simi-
larly. To get maximum bandwidth, C
F
is often set to form a
high frequency pole at the intersection of this increasing
noise gain and the open loop gain rolloff. This is accom-
plished by setting 1/2
π
(R
F
C
F
) equal to the geometric mean
of the zero frequency and the gain bandwidth product of the
op amp. If the gain bandwidth product is in Hz, and assum-
ing that C
F
<<
C
S
, C
F
may be calculated as:
FIGURE 5. Transimpedance Analysis Circuit.
FIGURE 6. Bode Analysis for Transimpedance Circuit.
C
F
=
1
R
F
2
π
GBWP
R
F
C
S
(
(
)
)
α
= R
F
C
S
GBW 2
π
(where C
S
= C
D
+ C
CM
+ C
DIFF
)
C
F
=
C
S
2
α
–1
α
C
S
2
α
F
–3dB
=
GBW
2
2
α
–1
α +
FIGURE 7. Compensation Capacitance vs Feedback
Resistance.
REQUIRED C
F
vs R
F
F
F
10
10
1
0.1
Transimpedance Gain, R
F
(k
)
100
1000
C
D
= 200pF
C
D
= 20pF
C
D
= 10pF
C
D
= 100pF
C
D
= 50pF
OPA655
R
F
C
F
C
DIFF
C
CM
C
D
I
DIODE
A
OL
Open Loop Gain
C
S
= C
D
+ C
DIFF
+ C
CM
Noise Gain
1
2
π
R
F
(C
S
+ C
F
)
0
1
2
π
R
F
C
F
Gain Bandwidth
Product
f (Hz)
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