參數(shù)資料
型號(hào)： OPA699IDR
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： Wideband, High Gain VOLTAGE LIMITING AMPLIFIER
中文描述： 寬帶，高增益電壓限幅放大器
文件頁(yè)數(shù)： 22/25頁(yè)
文件大小： 461K
代理商： OPA699IDR
OPA699
SBOS261B
22
www.ti.com
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 5 shows the general form for the
output noise voltage using the terms shown in Figure 16.
(5)
E
E
I
R
kTR
4
NG
I R
kTR NG
4
O
NI
BN
S
S
=
+
(
)
+
+
(
)
+
2
2
2
2
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input-referred spot noise voltage at
the noninverting input, as shown in Equation 6.
(6)
E
E
I
R
kTR
4
I R
NG
kTR
NG
N
NI
BN
S
S
F
=
+
(
)
+
+
+
2
2
2
4
Evaluating these two equations for the OPA699 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 27.4nV/
√
Hz
and a total equivalent input spot
noise voltage of 4.6nV/
√
Hz
. This total input-referred spot
noise voltage is only slightly higher than the 4.1nV/
√
Hz
specification for the op amp voltage noise alone. This will be
the case as long as the impedances appearing at each
op amp input are limited to a maximum value of 300
.
Keeping both (R
F
|| R
G
) and the noninverting input source
impedance less than 300
will satisfy both noise and
frequency response flatness considerations. Since the resis-
tor-induced noise is negligible, additional capacitive decoupling
across the bias current cancellation resistor (R
T
) for the
inverting op amp configuration of Figure 3 is not required, but
is still desirable.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a large variety of
applications. The power-supply current trim for the OPA699
gives even tighter control than comparable products. Al-
though the high-speed input stage does require relatively
high input bias current (typically 3
μ
A at each input terminal),
the close matching between them may be used to reduce the
output DC error caused by this current. The total output offset
voltage may be considerably reduced by matching the DC
source resistances appearing at the two inputs. This reduces
the output DC error due to the input bias currents to the offset
current times the feedback resistor. Evaluating the configura-
tion of Figure 1, using worst-case +25
°
C input offset voltage
and current specifications, gives a worst-case output offset
voltage, with NG = noninverting signal gain, equal to:
±
(NG
V
OS(MAX)
)
±
(R
F
I
OS(MAX)
)
=
±
(2
5mV)
±
(750
2.0
μ
A)
=
±
11.5mV
A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
of these techniques eventually reduce to adding a DC current
through the feedback resistor. In selecting an offset trim
method, one key consideration is the impact on the desired
signal path frequency response. If the signal path is intended
to be noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the signal
source. If the signal path is intended to be inverting, applying
the offset control to the noninverting input may be consid-
ered. However, the DC offset voltage on the summing
junction will set up a DC current back into the source which
must be considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
frequency response flatness. For a DC-coupled inverting
amplifier, Figure 17 shows one example of an offset adjust-
ment technique that has minimal impact on the signal fre-
quency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain as well as the frequency response.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with the high-frequency
OPA699 requires careful attention to layout design and
component selection. Recommended PCB layout techniques
and component selection criteria are:
a)
Minimize parasitic capacitance to any AC ground
for all
of the signal I/O pins. Open a window in the ground and
power planes around the signal I/O pins, and leave the
ground and power planes unbroken elsewhere.
b)
Provide a high quality power supply.
Use linear regu-
lators, ground plane and power planes to provide power.
Place high frequency 0.1
μ
F decoupling capacitors < 0.2"
away from each power-supply pin. Use wide, short traces to
connect to these capacitors to the ground and power planes.
Also use larger (2.2
μ
F to 6.8
μ
F) high-frequency decoupling
R
F
750
±
200mV Output Adjustment
=
–
R
–
5
G
Supply Decoupling
Not Shown
5k
5k
328
0.1
μ
F
R
G
150
V
I
20k
10k
0.1
μ
F
–
5V
+5V
OPA699
+5V
–
5V
V
O
V
O
V
I
R
F
FIGURE 17. DC-Coupled, Inverting Gain of
–
5, with Offset
Adjustment.
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