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參數(shù)資料
| 型號(hào)： | OR2C06A3S208I-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 144 CLBS, 6900 GATES, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁(yè)數(shù)： | 137/196頁(yè) |
| 文件大小： | 1393K |
| 代理商： | OR2C06A3S208I-DB |
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Lattice Semiconductor
45
Data Sheet
November 2006
ORCA Series 2 FPGAs
FPGA States of Operation (continued)
5-2761(F).r4
Figure 38. Start-Up Waveforms
Partial Reconguration
All
ORCA device families have been designed to allow
a partial reconguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
conguration sequence that tells the FPGA to not reset
all of the conguration RAM during a reconguration.
Then only the conguration frames that are to be modi-
ed need to be rewritten, thereby reducing the congu-
ration time.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconguration is being done. If this is done, the
user must be careful to not cause contention between
the two congurations (the bit stream resident in the
FPGA and the partial reconguration bit stream) as the
second reconguration bit stream is being loaded.
Other Conguration Options
Conguration options used during device start-up were
previously discussed in the FPGA States of Operation
section of this data sheet. There are many other cong-
uration options available to the user that can be set
during bit stream generation in ispLEVER. These
include options to enable boundary scan, readback
options, and options to control and use the internal
oscillator after conguration.
Other useful options that affect the next conguration
(not the current conguration process) include options
to disable the global set/reset during conguration, dis-
able the 3-state of I/Os during conguration, and dis-
able the reset of internal RAMs during conguration to
allow for partial congurations (see above). For more
information on how to set these and other conguration
options, please see the ispLEVER documentation.
Conguration Data Format
The ispLEVER development system interfaces with
front-end design entry tools and provides the tools to
produce a fully congured FPGA. This section dis-
cusses using the ispLEVER development system to
generate conguration RAM data and then provides
the details of the conguration frame format.
The
ORCA Series 2 series of FPGAs are enhanced
versions of the
ORCA ATT2Cxx/ATT2Txx architectures
that provide upward bit stream compatibility for both
series of devices as well as with each other.
Di
F
DONE
ATT3000
I/O
GLOBAL
RESET
C1
C2
C3
C4
F
C1
C2
C3
C4
C1
C2
C3
C4
C1, C2, C3, OR C4
Di + 1
Di
Di + 2
Di + 3
Di + 4
Di + 1
Di
Di + 2
Di + 3
Di + 4
ORCA CCLK_SYNC
DONE IN
U1
U2
U3
U4
F
U1
U2
U3
U4
U1
U2
U3
U4
ORCA UCLK_NOSYNC
Di + 1
Di
Di + 2
Di + 3
Di + 4
Di + 1
Di + 2
Di + 3
ORCA UCLK_SYNC
UCLK PERIOD
SYNCHRONIZATION UNCERTAINTY
DONE IN
F
C1
U1, U2, U3, OR U4
DONE
I/O
GSRN
ACTIVE
DONE
I/O
GSRN
ACTIVE
DONE
I/O
GSRN
ACTIVE
DONE
I/O
GSRN
ACTIVE
UCLK
F = finished, no more CLKs required.
CCLK PERIOD
F
ORCA CCLK_NOSYNC
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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| OR2C06A3S240I-DB | FPGA, 144 CLBS, 6900 GATES, PQFP240 |
| OR2C06A3T100I-DB | FPGA, 144 CLBS, 6900 GATES, PQFP100 |
| OR2C06A3T144I-DB | FPGA, 144 CLBS, 6900 GATES, PQFP144 |
| OR2C06A4T100-DB | FPGA, 144 CLBS, 6900 GATES, PQFP100 |
| OR2C15A-2B256 | FPGA, 400 CLBS, 15000 GATES, PBGA256 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C06A-3S240 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-3S240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A3S240I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 576 LUT 192 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C06A-3S256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2C06A-3S256I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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