參數(shù)資料
型號(hào)： OR2C08A-3M84
廠商： Electronic Theatre Controls, Inc.
元件分類(lèi)： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 143/192頁(yè)
文件大?。?/td> 3148K
代理商： OR2C08A-3M84
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54
Lucent Technologies Inc.
Data Sheet
ORCA Series 2 FPGAs
June 1999
Special Function Blocks (continued)
Boundary Scan
The increasing complexity of integrated circuits (ICs)
and IC packages has increased the difficulty of testing
printed-circuit boards (PCBs). To address this testing
problem, the
IEEE standard 1149.1 - 1990 (IEEE Stan-
dard Test Access Port and Boundary-Scan Architec-
ture) is implemented in the
ORCA series of FPGAs. It
allows users to efficiently test the interconnection
between integrated circuits on a PCB as well as test
the integrated circuit itself. The
IEEE 1149.1 standard
is a well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
The
IEEE 1149.1 standard defines a test access port
(TAP) that consists of a 4-pin interface with an optional
reset pin for boundary-scan testing of integrated cir-
cuits in a system. The
ORCA series FPGA provides
four interface pins: test data in (TDI), test mode select
(TMS), test clock (TCK), and test data out (TDO). The
PRGM
pin used to reconfigure the device also resets
the boundary-scan logic.
The user test host serially loads test commands and
test data into the FPGA through these pins to drive out-
puts and examine inputs. In the configuration shown in
Figure 47, where boundary scan is used to test ICs,
test data is transmitted serially into TDI of the first
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other configurations, mul-
tiple scan paths are used instead of a single ring. When
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.
Figure 48 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are
ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
Fig.34.a(F).1C
Key:
BSC = boundary-scan cell, BDC = bidirectional data cell,
and DCC = data control cell.
Figure 47. Printed-Circuit Board with Boundary-
Scan Circuitry
The boundary-scan support circuit shown in Figure 48
is the 497AA Boundary-Scan Master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general microprocessor interface
and provides parallel-to-serial/serial-to-parallel conver-
sion, as well as three 8K data buffers.
SCAN
OUT
TDI
TMS
TCK
TDO
U2
SEE ENLARGED VIEW BELOW
PLC
ARRAY
SCAN
IN
TDO TCK TMS TDI
TAPC
BYPASS
REGISTER
INSTRUCTION
REGISTER
BDC
BSC
P_IN
P_OUT
P_TS
SCAN
IN
PT[ij]
ENLARGED VIEW
TDI
TDO
TMS
TCK
U1
TDI
TDO
TMS
TCK
U4
TDI
TDO
TMS
TCK
U3
TDI
TDO
TMS
TCK
net a
net b
net c
s
DCC
SCAN
OUT
DCC
BSC
P_IN
P_OUT
P_TS
SCAN
IN
PB[ij]
BDC
SCAN
OUT
BDC
BSC
P_IN
P_OUT
P_TS
PR[ij]
DCC
SCAN
OUT
BSC
P_IN
P_OUT
P_TS
PL[ij]
SCAN
IN
DCC
BDC
相關(guān)PDF資料
PDF描述
OR2C08A-3M84I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 0.12uF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 1812; Termination: Solder Coated SnPb; Body Dimensions: 0.180" x 0.125" x 0.080"; Container: Bag; Features: MIL-PRF-55681: P Failure Rate
OR2C08A-3PS208 Field-Programmable Gate Arrays
OR2C08A-3PS208I Field-Programmable Gate Arrays
OR2C08A-3PS240 Field-Programmable Gate Arrays
OR2C08A-3PS240I Field-Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR2C08A3M84I-D 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use ECP/EC or XP LatticeXP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2C08A3S208I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 784 LUT 221 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2C08A3S240I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2C08A4BA256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
OR2C08A4J160-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 784 LUT 221 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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