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參數(shù)資料
| 型號(hào)： | OR2C10A-5T256I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 120/192頁 |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2C10A-5T256I |
Data Sheet
June 1999
ORCA Series 2 FPGAs
Lucent Technologies Inc.
33
Interquad Routing (continued)
In the hIQ block in Figure 29, the XH lines from one
quadrant connect through a CIP to its counterpart in
the opposite quadrant, creating a path that spans the
PLC array. Since a passive CIP is used to connect the
two XH lines, a 3-state signal can be routed on the two
XH lines in the opposite quadrants, and then they can
be connected through this CIP.
In the hIQ block, the 20 hIQ lines span the array in a
horizontal direction. The 20 hIQ lines consist of four
groups of five lines each. To effectively route nibble-
wide buses, each of these sets of five lines can connect
to only one of the bits of the nibble for both the XH and
XL. For example, hIQ0 lines can only connect to the
XH0 and XL0 lines, and the hIQ1 lines can connect
only to the XH1 and XL1 lines, etc. Buffers are provided
for routing signals from the XH and XL lines onto the
hIQ lines and from the hIQ lines onto the XH and XL
lines. Therefore, a connection from one quadrant to
another can be made using only two XH lines (one in
each quadrant) and one interquad line.
5-4537(F).r3
Figure 29. hIQ Block Detail
hIQ3[4]
hIQ3[3]
hIQ3[2]
hIQ3[1]
hIQ3[0]
hIQ2[4]
hIQ2[3]
hIQ2[2]
hIQ2[1]
hIQ2[0]
hIQ1[4]
hIQ1[3]
hIQ1[2]
hIQ1[1]
hIQ1[0]
hIQ0[4]
hIQ0[3]
hIQ0[2]
hIQ0[1]
hIQ0[0]
VXH[
3
]
VXH[
2
]
VXH[
1
]
VXH[
0
]
VXL
[3
]
VXL
[2
]
VXL
[1
]
VXL
[0
]
VX4
[7
]
VX4
[6
]
VX4
[5
]
VX4
[4
]
VX1
[7
]
VX1
[6
]
VX1
[5
]
VX1
[4
]
VX
4
[7
]
VX
4
[6
]
VX
4
[5
]
VX
4
[4
]
VX
1
[7
]
VX
1
[6
]
VX
1
[5
]
VX
1
[4
]
VX
H
[3
]
VX
H
[2
]
VX
H
[1
]
VX
H
[0
]
VX
L
[3
]
VX
L
[2
]
VX
L
[1
]
VX
L
[0
]
hIQ3[4]
hIQ3[3]
hIQ3[2]
hIQ3[1]
hIQ3[0]
hIQ2[4]
hIQ2[3]
hIQ2[2]
hIQ2[1]
hIQ2[0]
hIQ1[4]
hIQ1[3]
hIQ1[2]
hIQ1[1]
hIQ1[0]
hIQ0[4]
hIQ0[3]
hIQ0[2]
hIQ0[1]
hIQ0[0]
CA
RR
Y
CARR
Y
VX4
[3
]
VX4
[2
]
VX4
[1
]
VX4
[0
]
VX1
[3
]
VX1
[2
]
VX1
[1
]
VX1
[0
]
VX
1
[3
]
VX
1
[2
]
VX
1
[1
]
VX
1
[0
]
VX
4
[3
]
VX
4
[2
]
VX
4
[1
]
VX
4
[0
]
IN
T
[4
]
IN
T
[3
]
IN
T
[2
]
IN
T
[1
]
IN
T
[0
]
GS
R
N
CK
B
CK
T
INB
[4]
INB
[3]
INB
[2]
INB
[1]
INB
[0]
GS
R
N
CK
B
CK
T
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參數(shù)描述 |
|---|---|
| OR2C12A3BA256I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1296 LUT 288 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C12A3BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C12A3M84I-D | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1296 LUT 288 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C12A3S208-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1296 LUT 288 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C12A3S208-DBA1357 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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