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Data Sheet
June 1999
ORCA Series 2 FPGAs
Lucent Technologies Inc.
167
Timing Characteristics (continued)
Figure 72. Readback Timing Diagram
Table 54. Series 2 Readback Timing Characteristics
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C
≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C
≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,
–40 °C
≤ TA ≤ +85 °C.
Parameter
Symbol
Min
Max
Unit
RD_CFGN
to CCLK Setup Time
TS
50
—
ns
RD_CFGN
High Width to Abort Readback
TRBA
2—
CCLK
CCLK Low Time
TCL
50
—
ns
CCLK High Time
TCH
50
—
ns
CCLK Frequency
FC
—10
MHz
CCLK to RD_DATA Delay
TD
—50
ns
5-4536(F)
TD
TCH
CCLK
RD_DATA
TS
TCL
RD_CFGN
BIT 0
BIT 1
BIT 0
TRBA