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參數(shù)資料
| 型號(hào)： | OR2C12A-5M208I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 27pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated SnPb; Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 125/192頁(yè) |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2C12A-5M208I |
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38
Lucent Technologies Inc.
Data Sheet
ORCA Series 2 FPGAs
June 1999
Clock Distribution Network (continued)
5-4480(F).r3
Figure 34. Primary Clock Distribution
Secondary Clock
There are times when a primary clock is either not
available or not desired, and a secondary clock is
needed. For example:
s
Only one input pad per PIC can be placed on the
clock routing. If a second input pad in a given PIC
requires global signal routing, a secondary clock
route must be used.
s
Since there is only one branch driver in each PLC for
either direction (vertical and horizontal), both clock
lines in a particular row or column (CKL and CKR, for
example) cannot drive a branch. Therefore, two
clocks should not be placed into I/O pads in PICs on
the opposite sides of the same row or column if glo-
bal clocks are to be used.
s
Since the clock lines can only be driven from input
pads, internally generated clocks should use second-
ary clock routing.
Figure 35 illustrates the secondary clock distribution. If
the clock signal originates from either the left or right
side of the FPGA, it can be routed through the TRIDI
buffers in the PIC onto one of the adjacent PLC’s hori-
zontal XL lines. If the clock signal originates from the
top or bottom of the FPGA, the vertical XL lines are
used for routing. In either case, an XL line is used as
the clock spine. In the same manner, if a clock is only
going to be used in one quadrant, the XH lines can be
used as a clock spine. The routing of the clock spine
from the input pads to the VXL (VXH) using the BIDIs
(BIDIHs) is shown in Figure 35, Detail A.
In each PLC, a low-skew connection through a long-
line driver can be used to connect a horizontal XL line
to a vertical XL line or vice versa. As shown in Figure
35, Detail B, this is used to route the branches from the
clock spine. If the clock spine is a vertical XL line, then
the branches are horizontal XL lines and vice versa.
The clock is then routed into each PLC from the XL line
clock branches.
To minimize skew, the PLC clock input for all PLCs
must be connected to the branch XL lines, not the
spine XL line. Even in PLCs where the clock is routed
from the spine to the branches, the clock should be
routed back into the PLC from the clock branch.
If the clock is to drive only a limited number of loads,
the PFUs can be connected directly to the clock spine.
In this case, all flip-flops driven by the clock must be
located in the same row or column.
CKT
CKB
HXL
HCK
R7C8
HCK
DETAIL B
R7C7
HXL
CLOCK
BRANCH
CLOCK
SPINES
PLC R1C8
PLC R18C8
PIC PT8
CLOCK SPINE
CKT
DETAIL A
ABC
D
CLOCK
CLOCK SPINE
SEE DETAIL A
SEE DETAIL B
CLK PIN
BRANCHES
DT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C12A-5T208 | Field-Programmable Gate Arrays |
| OR2C12A-5T208I | Field-Programmable Gate Arrays |
| OR2C12A-5T240 | Field-Programmable Gate Arrays |
| OR2C12A-5T240I | Field-Programmable Gate Arrays |
| OR2C12A-5T256 | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| OR2C15A3BA256I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3M84I-D | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3PS240I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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