- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224637 > OR2C12A-5T240I (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號(hào)： | OR2C12A-5T240I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 134/192頁 |
| 文件大小： | 3148K |
| 代理商： | OR2C12A-5T240I |
Data Sheet
ORCA Series 2 FPGAs
June 1999
46
Lucent Technologies Inc.
Configuration Data Format (continued)
Table 9. Configuration Frame Format and Contents
Note:
For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must
be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive
integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit
stream generator tool supplies a bit stream which is compatible with all configuration modes, including slave parallel mode.
Header
11111111
Leading header—4 bits minimum dummy bits
0010
Preamble
24-Bit Length Count
Configuration frame length
1111
Trailing header—4 bits minimum dummy bits
ID Frame
(Optional)
0
Frame start
P—1
Must be set to 1 to indicate data frame
C—0
Must be set to 0 to indicate uncompressed
Opar, Epar
Frame parity bits
Addr[10:0] =
11111111111
ID frame address
Prty_En
Set to 1 to enable parity
Reserved [42:0]
Reserved bits set to 0
ID
20-bit part ID
111
Three or more stop bits (high) to separate frames
Configuration
Data
Frame
(repeated for
each data frame)
0
Frame start
P—1 or 0
1 indicates data frame; 0 indicates all frames are written
C—1 or 0
Uncompressed—0 indicates data and address are supplied;
Compressed—1 indicates only address is supplied
Opar, Epar
Frame parity bits
Addr[10:0]
Column address in FPGA to be written
A
Alignment bit (different number of 0s needed for each part)
1
Write bit—used in uncompressed data frame
Data Bits
Needed only in an uncompressed data frame
..
111
One or more stop bits (high) to separate frames
End of
Configuration
0010011111111111
16 bits—00 indicates all frames are written
Postamble
111111 . . . . .
Additional 1s
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2C12A-5T256 | Field-Programmable Gate Arrays |
| OR2C12A-5T256I | Field-Programmable Gate Arrays |
| OR2C12A-5T304I | Field-Programmable Gate Arrays |
| OR2C12A-5T352 | Field-Programmable Gate Arrays |
| OR2C12A-5T352I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2C15A3BA256I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3BA352I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3M84I-D | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2C15A3PS240I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 1600 LUT 298 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。