參數(shù)資料
型號(hào)： OR3C804BA352-DB
廠(chǎng)商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 484 CLBS, 116000 GATES, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 197/203頁(yè)
文件大?。?/td> 1368K
代理商： OR3C804BA352-DB
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Lattice Semiconductor
93
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Conguration Modes (continued)
There are two options for using the host interrupt
request in conguration mode. The conguration con-
trol register offers control bits to enable the interrupt on
either a bit stream error or to notify the host processor
when the FPGA is ready for more conguration data.
The MPI status register may be used in conjunction
with, or in place of, the interrupt request options. The
status register contains a 2-bit eld to indicate the bit
stream error status. As previously mentioned, there is
also a bit to indicate the MPI’s readiness to receive
another byte of conguration data. A ow chart of the
MPI
conguration process is shown in Figure 59. The
MPI
status and conguration register bit maps can be
found in the Special Function Blocks section and MPI
conguration timing information is available in the Tim-
ing Characteristics section of this data sheet.
5-5761(F)
Note: FPGA shown as a memory-mapped peripheral using CS0 and
CS1. Other decoding schemes are possible using CS0 and/or
CS1.
Figure 57.
PowerPC/MPI Conguration Schematic
5-5762(F)
Note: FPGA shown as only system peripheral with xed chip select
signals. For multiperipheral systems, address decoding and/or
latching can be used to implement chip selects.
Figure 58.
i960/MPI Conguration Schematic
Conguration readback can also be performed via the
MPI
when it is in user mode. The MPI is enabled in user
mode by setting the MP_USER bit to 1 in the congura-
tion control register prior to the start of conguration or
through a conguration option. To perform readback,
the host processor writes the 14-bit readback start
address to the readback address registers and sets the
RD_CFG
bit to 0 in the conguration control register.
Readback data is returned 8 bits at a time to the read-
back data register and is valid when the DATA_RDY bit
of the status register is 1. There is no error checking
during readback. A ow chart of the MPI readback
operation is shown in Figure 60. The RD_DATA pin
used for dedicated FPGA readback is invalid during
MPI
readback.
5-5763(F)
Figure 59. Conguration Through MPI
DOUT
CCLK
D[7:0]
A[4:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
CS0
CS1
HDC
LDC
D[7:0]
A[27:31]
CLKOUT
RD/WR
TA
BI
IRQx
TS
A26
A25
TO DAISY-
CHAINED
DEVICES
POWERPC
ORCA
8
FPGA
SERIES 3
DONE
INIT
DOUT
CCLK
D[7:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_IRQ
MPI_ALE
MPI_BE1
HDC
LDC
TO DAISY-
CHAINED
DEVICES
ORCA
8
FPGA
SERIES 3
DONE
INIT
AD[7:0]
CLKIN
W/R
RDYRCV
XINTx
ALE
BE1
i960
CS1
CS0
i960 SYSTEM CLOCK
VDD
MPI_BE0
BE0
MPI_STRB
ADS
POWER ON WITH
WRITE CONFIGURATION
READ STATUS REGISTER
INIT = 1?
NO
READ STATUS REGISTER
BIT STREAM ERROR?
DATA_RDY = 1?
WRITE DATA TO
DONE = 1?
DONE
ERROR
YES
NO
YES
NO
VALID M[3:0]
CONTROL REGISTER BITS
CONFIGURATION DATA REG
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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