參數(shù)資料
型號(hào)： ORLI10G-1BM680
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, MULTILAYER, BGA-680
文件頁數(shù)： 25/74頁
文件大?。?/td> 1411K
代理商： ORLI10G-1BM680
Agere Systems Inc.
31
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
ORLI10G Embedded PLLs
The ORLI10G embedded (transmit and receive) PLLs are based on the 4E series FPGA high-speed programma-
ble PLL. The 4E PLL consists of a phase/frequency detector (PFD), a charge pump/filter, a multitap voltage con-
trolled oscillator (VCO), a duty cycle synthesis circuitry, a power regulator, two programmable dividers, phase shift
selector multiplexers, a lock signal generator, and a current DAC. A block diagram of the programmable PLL is
shown in Figure 16. The receive path RX1_PLL and transmit path TX1_PLL, which can be programmed to create a
N/M frequency clock, are based on this design.
The receive path RX2_PLL and transmit path TX2_PLL create a X1 clock. This is essentially the same PLL without
the M and N divider.
The clock feedback loops for each PLL have been routed in the core so as to compensate for the routing delays to
the FPGA logic interface. In this way, the clock skew at the embedded core/FPGA logic boundary is zero for the
receive and transmit PLLs.
All PLLs include a phase shift selector which allows phase shift adjustments of each clock in increments of 1/8 the
period of the clock.
All functions of the embedded core PLLs are user controlled through a GUI provided with the ORLI10G Design Kit
software.
1331(F)
Figure 16. ORLI10G Programmable PLL Block Diagram
RCKI
M<5:0>
N<5:0>
SEL<2:0>
BYPASS
M
DIVIDER
N
DIVIDER
PFD
LOCK
GENERATOR
CHARGE PUMP
AND FILTER
VCO
PHASE
SELECT
RCKO
LOCK
VCOP
VCO
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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