參數(shù)資料
型號： ORLI10G-1BM680I
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, MULTILAYER, BGA-680
文件頁數(shù)： 32/74頁
文件大小： 1411K
代理商： ORLI10G-1BM680I
38
Agere Systems Inc.
Preliminary Data Sheet
March 2001
10 Gbits/s Transmit and Receive Line Interface
ORCA ORLI10G FPSC
Timing Characteristics
Receive/Transmit Input Data/Sync Interface
Receive (Line)/Transmit (System) STS-48/STS-192 (2.5G/10G) Data Inputs
Figure 19 illustrates the timing for the receive (line) and transmit (system) STS-48/STS-192 data stream. Both the
clock and data pins are low-voltage differential signal (LVDS) input buffers. The expected clock rate is 622.08 MHz/
666.51428 MHz and the receive/transmit data is clocked on the rising edge of the clock. In 2.5G (divide-by-8)
mode, each of the four channels uses one set of RX_CLK_IN_n and 4 RX_DAT_IN_n data pins. In 10G (divide-by-
4) mode, only RX_CLK_IN_0 and TX_CLK_IN is used, along with theRX_DAT_IN_[15:0] pins.
Both the clock and frame sync are low-voltage differential signal (LVDS) input buffers. The expected clock is
622.08 MHz—666.51 MHz. It is recommended that the Rx clock be inverted by crossing the LVDS pin pair, that is,
connect the N to the P and the P to the N. This is because the embedded LI requires the Rx data to be centered on
the Rx clock. The timing values for the diagram are given in Table 13.
5-9085.b (F)
Figure 19. Receive/Transmit Data Timing
Table 13. Receive (Line)/Transmit (System) Data Timing
Symbol
Parameter
Min
Typ
Max
Unit
t1
Clock Period
—
1608/1500
—
ps
t2
Data Setup Time Required
300
——
ps
t3
Data Hold Time Required
300
——
ps
RX_CLK_IN_[3:0],
RX_DATA_IN_[15:0],
P
N
P
N
t1
t3
t2
TX_CLK_IN
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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